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Assessment of Interface Trap Charges on Proposed TFET for Low Power High-Frequency Application

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Abstract

Accumulation of trap charges at the semiconductor and oxide interface is the most dominating factor and cannot be neglected as it degrades device performance and reliability. This manuscript, presents detailed investigation to analyze the impact of interface trap charges (ITCs) on the performance parameters of the proposed device i.e., heterogeneous dielectric dual metal gate step channel TFET (HD DMG SC-TFET). The comparative study is conducted with dual metal gate step channel TEFT (DMG SC-TFET). The proposed device shows improved current carrying capability, suppressed ambipolar behaviour with steeper subthreshold swing. The purpose of this study to determine the ITCs impact on DC characteristics and analog/RF electrical performance parameters of the proposed device. It further observed that the proposed device exhibit superior performance due to dielectric engineering at oxide layer. Moreover, advanced communication devices must respond linearly therefore, the impact of ITCs on linearity parameters is also studied. From this brief comparative investigation, it is observed that the proposed TFET exhibits negligible distortion in linearity parameters with little or no impact of trap charges as compared to DMG SC-TFET. Thus, proposed TFET is appropriate for ultra-low power high-frequency electronic devices.

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Acknowledgements

The authors would like to thank Dr. Dip Prakash Samajdar from Department of Electronics and Communication Engineering, PDPM Indian Institute of Information Technology, Design & Manufacturing, Jabalpur, Madhya Pradesh, India for providing valuable suggestions and support to carry out this research work.

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Authors and Affiliations

  1. National Institute of Technology Hamirpur, Himachal Pradesh, 177005, India

    Sachin Kumar & Dharmendra Singh Yadav

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  1. Sachin Kumar
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  2. Dharmendra Singh Yadav
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Contributions

Sachin Kumar: Conceptualization, data curation, formal analysis, methodology, investigation, writing - original draft. Dharmendra Singh Yadav: Supervision, validation, visualization, writing - review & editing.

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Kumar, S., Yadav, D.S. Assessment of Interface Trap Charges on Proposed TFET for Low Power High-Frequency Application. Silicon 14, 9291–9304 (2022). https://doi.org/10.1007/s12633-021-01616-0

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