Abstract
In this ultramodern scenario, low power, less cost and reduced storage devices are in great demand. Because the majority devices operate on a remote power supply, low-power memories are enticing the unified VLSI industry. For reduced power consumption, high energy efficiency circuit, TFET is a feasible alternate to MOSFET as it is a p-type, intrinsic, n-type (p-i-n) diode whose tunnel current drifts amidst of the bands of channel and source having a minimum leakage current and reduced sub-threshold slope (SS). The sole difference between TFET and MOSFET is the switching mechanism: TFETs use band-to-band tunnelling (BTBT), while MOSFETs use thermionic emission. In this survey, various types of TFET structures are described considering analog, linearity and device parameters like on-current (ION), SS, off-current (IOFF), current ratio (ION/IOFF), threshold voltage (VT) etc., and comparison is done among the designed TFET structures.
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References
Saurabh S, Kumar MJ (2016) Fundamentals of tunnel field-effect transistors. 1st Edition. CRC Press. https://doi.org/10.1201/9781315367354
Saxena S, Tripathi SL, Sinha SK, Patel GS, Pravalika C (2019) Review on performance evaluation of TFET Structures & its Applications. THINK INDIA J 22(16):220–227
Schaller RR (1997) Moore’s law: past, present and future. IEEE Spectr 34(6):52–59
Reddy NN, Panda DK (2020) A comprehensive review on tunnel field-effect transistor (TFET) based biosensors: recent advances and future prospects on device structure and sensitivity. Silicon. https://doi.org/10.1007/s12633-020-00657-1
Datta S, Liu H, Narayan V (2014) Tunnel FET tech.: a reliability perspective. Microelectron Reliabil 54(5):861–874
Strangio S, Settino F, Palestri P, Lanuzza M, Crupi F, Esseni D, Selmi L (2018) Digital and analog TFET circuits: design and benchmark. Solid State Electron 146:50–65. https://doi.org/10.1016/j.sse.2018.05.003
Satish T, Kureshi AK (2016) Review of tunnel field effect transistor (TFET). Int J Appl Eng Res 11(7):4922–4929
Fahad HM, Hussain MM (2013) High-performance Si nanotube tunneling FET for ultralow-power logic applications. IEEE Trans. on Electron Dev. 60(3):1034–1039
Kumar MJ, Janardhanan S (2013) Doping-less Tunnel Field Effect Transistor: Design and Investigation. IEEE Trans on Electron Dev 60(10):3285-3290
Hanna AN, Hussain MM (2015) Si/Ge hetero-structure nanotube tunnel field effect transistor. J Appl Phys 117(1):1–7. https://doi.org/10.1063/1.4905423
Seo JH, Yoon YJ, Lee S, Lee JH, Cho S, Kang IM (2015) Design and analysis of Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET). Current Appl Phys 15(3):208–212
Nigam K, Pandey S, Kondekar PN, Sharma D (2016) Temperature sensitivity analysis of polarity controlled electrically doped hetero-TFET. 12th Conf. on Ph.D. Res. in Microelectron. and Electron. (PRIME). 1–4. https://doi.org/10.1109/PRIME.2016.7519465
Madan J, Chaujar R (2016) Gate drain-overlapped-asymmetric gate dielectric-GAA-TFET: a solution for suppressed ambipolarity and enhanced ON state behaviour. Appl Phys A Mater Sci Process 122:973. https://doi.org/10.1007/s00339-016-0510-0
Gupta S, Nigam K, Pandey S, Sharma D, Kondekar PN (2017) Performance improvement of heterojunction double gate drain overlapped TFET using Gaussian doping. Fifth Berk. Sym. On Energ. Effi. Electron. Sys. & steep transistors. Work. E3S:1–3. https://doi.org/10.1109/e3s.2017.8246171
Li W, Liu H, Wang S, Chen S, Yang Z (2017) Design of High Performance Si/SiGe HeterojunctionTunneling FETs with a T-shaped gate. Nanoscale Res Lett 12:198. https://doi.org/10.1186/s11671-017-1958-3
Soni D, Sharma D, Yadav S, Aslam M, Sharma N (2018) Performance improvement of doped TFET by using plasma formation concept. Superlattice Microst 113:97–109. https://doi.org/10.1016/j.spmi.2017.10.012
Sahay S, Kumar MJ (2017) Nanotube Junctionless FET: proposal, design, and investigation. IEEE Trans. on Electron Dev. 64(4):1851–1856. https://doi.org/10.1109/TED.2017.2672203
Singh S, Pal P, Mittal R, Tamia A, Kondekar PN (2014) Si on ferroelectric tunnel FET (SOF-TFET) for low power application. IEEE 2nd Int. Conf. on Emer. Electron. (ICEE). 1–3. https://doi.org/10.1109/icemelec.2014.7151189
Raad BR, Tirkey S, Dheeraj Sharma D, PravinKondekar P (2017) A new design approach of Dopingless tunnel FET for enhancement of device characteristics. IEEE Trans Electron Dev 64(4):1830–1836
Yadav S, Madhukar R, Sharma D, Aslam M (2018) A new structure of electrically doped TFET for improving electronic characteristics. Appl Phys 124(7):517. https://doi.org/10.1007/s00339-018-1930-9
Kumar N, Mushtaq U, Amin I, Anand S (2019) Design and performance analysis of dual-gate all around Core-Shell nanotube TFET. Superlattice Microst 125:356–364. https://doi.org/10.1016/j.spmi.2018.09.012
Singh S, Ashish Raman A (2018) A dopingless gate-all-around (GAA) gate-stacked nanowire FET with reduced parametric fluctuation effects. J Comp Electron 17:967–976. https://doi.org/10.1007/s10825-018-1166-0
Dutta U, Soni MK, Pattanaik M (2018) Design and analysis of tunnel FET for low power high performance applications. Int J Mod Edu Comp Sci 10(1):65–73. https://doi.org/10.5815/ijmecs.2018.01.07
Kim JH, Kim S, Park B (2019) Double-gate TFET with Vertical Channel sandwiched by lightly doped Si. IEEE Trans on Electron Dev 66(4):1656–1661
Singh A, Chaudhary S, Sharma SM, Sarkar CK (2020) Improved drive capability of silicon Nano tube tunnel FET using halo implantation. Silicon. 12:2555–2561. https://doi.org/10.1007/s12633-019-00350-y
Musalgaonkar G, Sahay S, Saxena RS, Kumar MJ (2020) Nanotube tunneling FET with a Core source for Ultrasteep subthreshold swing: a simulation study. IEEE Trans on Elect Dev 66(10):4425–4432
Shreya S, Khan AH, Kumar N, Amin SI, Anand S (2019) Core-Shell Junctionless nanotube tunnel field effect transistor: design and sensitivity analysis for biosensing application. IEEE Sensors J 20(2):672–679
Musalgaonkar G, Sahay S, Saxena RS, Kumar MJ (2019) A Line Tunneling Field-Effect Transistor Based on Misaligned Core–Shell Gate Architecture in Emerging Nanotube FETs IEEE Trans. on Elect Dev 66(6): 2809–2816
Patel J, Sharma D, Yadav S, Lemtur A, Suman P (2019) Performance improvement of nanowire TFET by hetero-dielectric and hetero-material: at device and circuit level. Microelectron J 85:72–82
Mushtaq U, Kumar N, Anand S, Amin I (2019) Design and performance analysis of Core-Shell dual metal-dual gate cylindrical GAA silicon nanotube-TFET. Silicon. 12:2355–2363. https://doi.org/10.1007/s12633-019-00329-9
Wadhwa G, Kamboj P, Raj B (2019) Design optimisation of junctionless TFET biosensor for high sensitivity. Adv Nat Sci Nanosci Nanotechnol 10(4):1–7. https://doi.org/10.1088/2043-6254/ab4878
Yun S, Oh J, Seokjung Kang S, Kim Y, Kim JH, Kim G, Kim S (2019) F-shaped tunnel field-effect transistor (TFET) for the low-power application. Micromachines. 10(11):1–10. https://doi.org/10.3390/mi10110760
Gupta AK, Raman A, Kumar N (2019) Design and investigation of a novel charge plasma-based Core-Shell ring-TFET: analog and linearity analysis. IEEE Trans. on Electron Dev. 66(8):3506–3512
Agha FNAK, Hashim Y, Shakib MN (2020) Temperature Impact on The ION/IOFF Ratio of Gate All Around Nanowire TFET. IEEE Int. Conf. on Semiconductor Electron. (ICSE). 61–64. https://doi.org/10.1109/icse49846.2020.9166887
Gupta AK, Raman A (2020) Electrostatic-doped nanotube TFET: proposal, design and investigation with linearity analysis. Silicon. 13:2401–2413. https://doi.org/10.1007/s12633-020-00584-1
Shekhar D, Raman A (2020) Design and analysis of dual-gate misalignment on the performance of dopingless tunnel field effect transistor. Appl Phys A Mater Sci Process 126(441):1–9. https://doi.org/10.1007/s00339-020-03615-1
Vimala P, Sharma SS, Krishna LL, Bassapuri M, Manikanta T (2020) Characteristic analysis of Si nanowire tunnel field effect transistor (NW-TFET). IEEE Int. Conf. on Electron. Comp. and Commun. Tech. (CONECCT). 1–4. https://doi.org/10.1109/CONECCT50063.2020.9198578
Apoorva, Kumar N, Amin SI, Anand S (2020) Design and performance optimization of novel Core–Shell Dopingless GAA-nanotube TFET with Si0.5Ge0.5- based source. IEEE Trans Elect Dev 67(3):789–795
Sharma M, Narang R, Saxena M, Gupta M (2020) Optimized DL-TFET Design for Enhancing its performance parameters by using different engineering methods. IETE Tech Rev 1-9. https://doi.org/10.1080/02564602.2020.1758226
Gedam A, Acharya B, Mishra GP (2021) Junctionless silicon nanotube TFET for improved DC and radio frequency performance. Silicon. 13:167–178. https://doi.org/10.1007/s12633-020-00410-8
Kumar S, Yadav DS, Saraswat S, Parmar N, Sharma R, Kumar A (2020) A novel Step-Channel TFET for better subthreshold swing and improved analog/RF characteristics. IEEE Int. Stu' Conf. on Elec., Electron. and Com. Sci. (SCEECS). 1–6. https://doi.org/10.1109/sceecs48394.2020.104
Verreck D, Groeseneken G, Verhulst A (2016) The tunnel-field effect transistor. Wiley encyclopedia of electrical and electronics engineering. Wiley. https://doi.org/10.1002/047134608X.W8333
Gupta AK, Raman A (2020) Performance analysis of electrostatic plasma based dopingless nanotube TFET. Appl Phys A Mater Sci Process 126(7):573. https://doi.org/10.1007/s00339-020-03736-7
Acknowledgements
The authors would like to thank Mr. G. V. M. Mohan Kumar, Chairman of G. Pullaiah College of Engineering and Technology, Kurnool, India, for encouragement and support during the present research work.
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Alluru Sreevani: Investigation; Formal analysis, Writing - original draft. Sandip Swarnakar: Conceptualization; Investigation; Formal analysis, Writing - original draft, Supervision. Sabbi Vamshi Krishna: Validation; Writing - review & editing.
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Sreevani, A., Swarnakar, S. & Krishna, S.V. Comparative Study of Analog Parameters for Various Silicon-Based Tunnel Field-Effect Transistors. Silicon 14, 9223–9235 (2022). https://doi.org/10.1007/s12633-022-01674-y
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DOI: https://doi.org/10.1007/s12633-022-01674-y