Skip to main content
Log in

Evolution of Tunnel Field Effect Transistor for Low Power and High Speed Applications: A Review

  • Review Paper
  • Published:
Silicon Aims and scope Submit manuscript

Abstract

Various challenges arise in a continuous scaling of MOSFET like Short Channel Effects, as the channel length shrinks, current is produced in OFF-state, which also results in high leakage current and power dissipation and limits the Sub-threshold Swing (SS) upto 60mV/decade. To reduce these limitations in MOSFET, new MOS devices should be developed to continue scaling. Tunnel Field Effect transistor (TFET) is the promising device suitable to replace the conventional MOSFET. A review on Tunnel field effect transistors (TEFT) to reduce the limitations and overcome the challenges of the conventional MOSFET device are presented in this paper. Various TFET structures with different doping concentrations and materials are discussed to enhance the performance of the device. TFET is suitable for analog applications and radio frequency application because of its high ON state current, low ambipolar current, low SS and low threshold voltage.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

Data Availability

Yes the data andmaterial is available.

References

  1. Frank DJ, Dennard RH, Nowak E et al (2001) Device scaling limits of Si MOSFETs and their application dependencies. Proc IEEE 89:259–287. https://doi.org/10.1109/5.915374

    Article  CAS  Google Scholar 

  2. Zeitzoff PM, Huff HR (2005) MOSFET scaling trends, challenges, and key associated metrology issues through the end of the roadmap. AIP Conf Proc 788:203–213. https://doi.org/10.1063/1.2062964

    Article  CAS  Google Scholar 

  3. Taur Y, Buchanan DA, Chen W et al (1997) CMOS scaling into the nanometer regime. Proc IEEE 85:486–503. https://doi.org/10.1109/5.573737

    Article  Google Scholar 

  4. Chaudhry A, Kumar MJ (2004) Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: A review. IEEE Trans Device Mater Reliab 4:99–109. https://doi.org/10.1109/TDMR.2004.824359

    Article  Google Scholar 

  5. Pearce CW, Yaney DS (1985)Short-channel effects in MOSFET’s. IEEE Electron Device Lett 6:326–328. https://doi.org/10.1109/EDL.1985.26143

    Article  Google Scholar 

  6. Qu JT, Zhang HM, Xu XB, Qin SS (2011) Study of Drain Induced Barrier Lowering(DIBL) effect for strained Si nMOSFET. Procedia Eng 16:298–305. https://doi.org/10.1016/j.proeng.2011.08.1087

    Article  CAS  Google Scholar 

  7. PATI GS (2014) Two dimensional analytical thresholg voltage modeling of dual material gate S-SOI MOSFET. National Institute of Technology, Rourkela

    Google Scholar 

  8. D’Agostino F, Quercia D (2000)Short-channel effects in MOSFETs. Intro VLSI Des 467(70):71–72

  9. Wei HW, Ruslan SH (2019) Investigation of FDSOI and PDSOI MOSFET characteristics. AIP Conf Proc 2173. https://doi.org/10.1063/1.5133920

  10. Cheng K, Khakifirooz A (2016) Fully depleted SOI (FDSOI) technology. Sci China Inf Sci 59:1–15. https://doi.org/10.1007/s11432-016-5561-5

    Article  Google Scholar 

  11. Ekta Goel S, Kumar K, Singh B, Singh M, Kumar, Student Member I, Jit S, Member I (2016)2-D analytical modeling of threshold voltage for graded-channel dual-material double-gate MOSFETs. IEEE Trans Electron Devices 63:8

  12. Goel E, Kumar S, Singh B et al (2017)Two-dimensional model for subthreshold current and subthreshold swing of graded-channel dual-material double-gate(GCDMDG) MOSFETs. Superlattices Microstruct 106:147–155. https://doi.org/10.1016/j.spmi.2017.03.047

    Article  CAS  Google Scholar 

  13. Goel E, Singh B, Kumar S et al (2017) Analytical threshold voltage modeling of ion-implanted strained-Si double-material double-gate (DMDG) MOSFETs. Indian J Phys 91:383–390. https://doi.org/10.1007/s12648-016-0918-6

    Article  CAS  Google Scholar 

  14. Tripathi SL (2020) Low power high performance. Multi-Gate Mosfet Structures 16:209–219

  15. Long W, Ou H, Kuo J, Chin KK (1999)Dual-Material Gate (DMG) field effect transistor. IEEE Trans Electron Devices 46:865–870

  16. Keerti Kumar K, Bheema Rao N (2012) Variable gate oxide thickness MOSFET: A device level solution for sub-threshold leakage current reduction. 2012 Int Conf Devices, Circuits Syst ICDCS 2012, 495–498. https://doi.org/10.1109/ICDCSyst.2012.6188765

  17. Chaudhary R, Mukhiya R, Patel GS et al (2018) Simulation of MOSFET with different dielectric films. Proc – 2nd Int Conf Intell Circuits Syst ICICS 2018, 177–183. https://doi.org/10.1109/ICICS.2018.00044

  18. Feldbaumer DW, Schroder DK (1991) MOSFET doping profiling. IEEE Trans Electron Devices 38:135–140. https://doi.org/10.1109/16.65747

    Article  Google Scholar 

  19. Yadav VK, Rana AK (2012) Impact of channel doping on DG-MOSFET parameters in Nano regime-TCAD simulation. Int J Comput Appl 37:36–41

    Google Scholar 

  20. Hoyt JL, Nayfeh HM, Eguchi S et al (2002) Strained silicon MOSFET technology. Tech Dig - Int Electron Devices Meet, 23–26. https://doi.org/10.1109/IEDM.2002.1175770

  21. Verdonckt-vandebroek S, Crabbc EF, Meyerson BS et al (1994) S iGe-Channel Heteroj unc tion p-MOSFET ’ s. 41:90–101

  22. Pandey A (2022) Recent trends in novel semiconductor devices. Silicon. https://doi.org/10.1007/s12633-022-01694-8

  23. Aswathy M, Biju NM, Komaragiri R (2012) Simulation studies of tunnel field effect transistor (TFET). Proc – 2012 Int Conf Adv Comput Commun ICACC 2012, 138–141. https://doi.org/10.1109/ICACC.2012.31

  24. Turkane SM, Kureshi AK (2016) Review of tunnel field effect transistor (TFET). Int J Appl Eng Res 11:4922–4929

    Google Scholar 

  25. Choi WY, Park BG, Lee JD, Liu TJK (2007) Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett 28:743–745. https://doi.org/10.1109/LED.2007.901273

    Article  CAS  Google Scholar 

  26. Agopian PG, Der, Martino MDV, Filho SGDS et al (2012) Temperature impact on the tunnel fet off-state current components. Solid State Electron 78:141–146. https://doi.org/10.1016/j.sse.2012.05.053

    Article  CAS  Google Scholar 

  27. Boucart K, Ionescu AM (2007)Double-gate tunnel FET with high-κ gate dielectric. IEEE Trans Electron Devices 54:1725–1733. https://doi.org/10.1109/TED.2007.899389

    Article  CAS  Google Scholar 

  28. Singh A, Chaudhury S, Pandey CK et al (2019) Design and analysis of high k silicon nanotube tunnel FET device. IET Circuits Devices Syst 13:1305–1310. https://doi.org/10.1049/iet-cds.2019.0230

    Article  Google Scholar 

  29. Ranjan R, Junarao M, Pradhan KP, Sahu PK (2016) A comprehensive investigation of silicon film thickness (TSI) of nanoscale DG TFET for low power applications. Adv Nat Sci Nanosci Nanotechnol 7. https://doi.org/10.1088/2043-6262/7/3/035009

  30. Boucart K, Ionescu AM (2006) Double gate tunnel FET with ultrathin silicon body and high-k gate dielectric. ESSDERC 2006 - Proc 36th Eur Solid-State. Device Res Conf 383–386. https://doi.org/10.1109/ESSDER.2006.307718

  31. Min J, Wu J, Taur Y (2015) Analysis of source doping effect in tunnel FETs with staggered bandgap. IEEE Electron Device Lett 36:1094–1096. https://doi.org/10.1109/LED.2015.2466676

    Article  CAS  Google Scholar 

  32. Vijayvargiya V, Vishvakarma SK (2014) Effect of drain doping profile on double-gate tunnel field-effect transistor and its influence on device RF performance. IEEE Trans Nanotechnol 13:974–981. https://doi.org/10.1109/TNANO.2014.2336812

    Article  CAS  Google Scholar 

  33. Tiwari S, Saha R (2021) Methods to reduce ambipolar current of various TFET structures: a review. Silicon. https://doi.org/10.1007/s12633-021-01458-w

  34. Sahay S, Kumar MJ (2015) Controlling the drain side tunneling width to reduce ambipolar current in tunnel FETs using Heterodielectric BOX. IEEE Trans Electron Devices 62:3882–3886. https://doi.org/10.1109/TED.2015.2478955

    Article  Google Scholar 

  35. Poria S, Garg S, Saurabh S (2020) Suppression of ambipolar current in tunnel field-effect transistor using field-plate. 2020 24th Int Symp VLSI Des Test, VDAT 2020 1:5–10. https://doi.org/10.1109/VDAT50263.2020.9190409

  36. Pandey P, Vishnoi R, Kumar MJ (2014) Drain current model for SOI TFET considering source and drain side tunneling. 2014 IEEE 2nd Int Conf Emerg Electron Mater to Devices, ICEE 2014 - Conf Proc. https://doi.org/10.1109/ICEmElec.2014.7151203

  37. Lee MJ, Choi WY (2011) Analytical model of single-gatesilicon-on-insulator(SOI) tunneling field-effect transistors (TFETs). Solid State Electron 63:110–114. https://doi.org/10.1016/j.sse.2011.05.008

    Article  CAS  Google Scholar 

  38. Pandey CK, Dash D, Chaudhury S (2020) Improvement in analog/RF performances of SOI TFET using dielectric pocket. Int J Electron 107:1844–1860. https://doi.org/10.1080/00207217.2020.1756439

    Article  Google Scholar 

  39. Chander S, Sinha SK, Kumar S et al (2017) Temperature analysis of Ge/Si heterojunction SOI-Tunnel FET. Superlattices Microstruct 110:162–170. https://doi.org/10.1016/j.spmi.2017.08.048

    Article  CAS  Google Scholar 

  40. Pindoo I, Sinha SK, Chander S (2021) Analog / RF performance analysis of heterojunction tunnel FET with temperatute. 1–13. https://doi.org/10.21203/rs.3.rs-298331/v1

  41. Arun Samuel TS, Balamurugan NB, Bhuvaneswari S et al (2014) Analytical modelling and simulation of single-gate SOI TFET for low-power applications. Int J Electron 101:779–788. https://doi.org/10.1080/00207217.2013.796544

    Article  CAS  Google Scholar 

  42. Mitra SK, Goswami R, Bhowmick B (2015) Optimization and scaling of an SOI TFET with back gate control. 2015 Int Conf Recent Dev Control Autom Power Eng RDCAPE 2015 7–9. https://doi.org/10.1109/RDCAPE.2015.7281360

  43. Guenifi N, Rahi SB, Ghodbane T (2019) Rigorous study of double gate tunneling field effect transistor structure based on silicon. Mater Focus 7:866–872. https://doi.org/10.1166/mat.2018.1600

    Article  CAS  Google Scholar 

  44. Ramaswamy S, Kumar MJ (2017) Double gate symmetric tunnel FET: Investigation and analysis. IET Circuits. Devices Syst 11:365–370. https://doi.org/10.1049/iet-cds.2016.0324

    Article  Google Scholar 

  45. Mallikarjunarao, Ranjan R, Pradhan KP, Sahu PK (2016) Dielectric engineered symmetric underlap double gate tunnel FET (DGTFET): An investigation towards variation of dielectric materials. Superlattices Microstruct 96:226–233. https://doi.org/10.1016/j.spmi.2016.05.035

    Article  CAS  Google Scholar 

  46. Vishnoi R, Kumar MJ (2014) Compact analytical model of dual material gate tunneling field-effect transistor using interband tunneling and channel transport. IEEE Trans Electron Devices 61:1936–1942. https://doi.org/10.1109/TED.2014.2315294

    Article  CAS  Google Scholar 

  47. Pandey P, Vishnoi R, Kumar MJ (2015) A full-range dual material gate tunnel field effect transistor drain current model considering both source and drain depletion region band-to-band tunneling. J Comput Electron 14:280–287. https://doi.org/10.1007/s10825-014-0649-x

    Article  Google Scholar 

  48. Kumar S, Goel E, Singh K et al (2016) A Compact 2-D Analytical Model for Electrical Characteristics of Double-Gate Tunnel Field-Effect Transistors with a SiO2/High-k Stacked Gate-Oxide Structure. IEEE Trans Electron Devices 63:3291–3299. https://doi.org/10.1109/TED.2016.2572610

    Article  CAS  Google Scholar 

  49. Kumar S, Goel E, Singh K et al (2017)2-D analytical modeling of the electrical characteristics of dual-material double-gate TFETs with a SiO2/HfO2 stacked gate-oxide structure. IEEE Trans Electron Devices 64:960–968. https://doi.org/10.1109/TED.2017.2656630

    Article  CAS  Google Scholar 

  50. Kumar S, Singh K, Chander S et al (2018)2-D analytical drain current model of double-gate heterojunction TFETs with a SiO2/HfO2 stacked gate-oxide structure. IEEE Trans Electron Devices 65:331–338. https://doi.org/10.1109/TED.2017.2773560

    Article  CAS  Google Scholar 

  51. Singh P, Samajdar DP, Yadav DS (2021) Doping and dopingless tunnel field effect transistor. 2021 6th Int Conf Converg Technol I2CT 2021, 1–7. https://doi.org/10.1109/I2CT51068.2021.9418076

  52. Kumar MJ, Janardhanan S (2013)Doping-less tunnel field effect transistor: Design and investigation. IEEE Trans Electron Devices 60:3285–3290. https://doi.org/10.1109/TED.2013.2276888

    Article  CAS  Google Scholar 

  53. Kumar S, Raj B, Raj B (2021)Dual-material gate-drain overlapped DG-TFET device for low leakage current design. Silicon 13:1599–1607. https://doi.org/10.1007/s12633-020-00547-6

    Article  CAS  Google Scholar 

  54. Pandey CK, Singh A, Chaudhury S (2020) Effect of asymmetric gate–drain overlap on ambipolar behavior of double-gate TFET and its impact on HF performances. Appl Phys A Mater Sci Process 126:1–12. https://doi.org/10.1007/s00339-020-3402-2

    Article  CAS  Google Scholar 

  55. Mohammadi S, Khaveh HRT (2017) An analytical model for double-gate tunnel FETs considering the junctions depletion regions and the channel mobile charge carriers. IEEE Trans Electron Devices 64:1276–1284. https://doi.org/10.1109/TED.2017.2655102

    Article  Google Scholar 

  56. Kumar S, Singh KS, Nigam K et al (2019)Dual-material dual-oxide double-gate TFET for improvement in DC characteristics, analog/RF and linearity performance. Appl Phys A Mater Sci Process 125:1–8. https://doi.org/10.1007/s00339-019-2650-5

    Article  CAS  Google Scholar 

  57. Kumar S, Nigam K, Chaturvedi S et al (2021) Performance improvement of double-gate TFET using metal strip technique. Silicon. https://doi.org/10.1007/s12633-021-00982-z

  58. Zhang M, Guo Y, Zhang J et al (2020) Simulation study of the double-gate tunnel field-effect transistor with step channel thickness. Nanoscale Res Lett 15. https://doi.org/10.1186/s11671-020-03360-7

  59. Sneh S, Kumar MJ (2009) Impact of strain on drain current and threshold voltage of nanoscale double gate tunnel field effect transistor: Theoretical investigation and analysis. Jpn J Appl Phys 48:1–35. https://doi.org/10.1143/JJAP.48.064503

    Article  CAS  Google Scholar 

  60. Kumar MJ, Saurabh S (2008) Tunnel Field Effect Transistor (TFET) with strained silicon thinfilm body for enhanced drain current and pragmatic threshold voltage. Tech Proc 2008 NSTI Nanotechnol Conf Trade Show, NSTI-Nanotech. Nanotechnol 2008 3:28–30

    CAS  Google Scholar 

  61. Abdi DB, Jagadesh Kumar M (2015) PNPN tunnel FET with controllable drain side tunnel barrier width: Proposal and analysis. Superlattices Microstruct 86:121–125. https://doi.org/10.1016/j.spmi.2015.07.045

    Article  CAS  Google Scholar 

  62. Chander S, Sinha SK, Kumar S et al (2018) Performance evaluation of heterojunction SOI-tunnel FET with temperature. 2017 14th IEEE India Counc Int Conf INDICON 2017, 4–8. https://doi.org/10.1109/INDICON.2017.8487657

  63. Singh B, Nath T, Gola D et al (2017)Ferro-electric stacked gate oxide heterojunction electro-statically doped source / drain double-gate tunnel field effect transistors. A superior structure. 71:161–165. https://doi.org/10.1016/j.mssp.2017.07.014

  64. Dash DK, Saha P, Sarkar SK (2018) Analytical modeling of asymmetric hetero-dielectric engineered dual-material DG-TFET. J Comput Electron 17:181–191. https://doi.org/10.1007/s10825-017-1102-8

    Article  CAS  Google Scholar 

  65. Ghosh B, Akram MW (2013) Junctionless tunnel field effect transistor. IEEE Electron Device Lett 34:584–586. https://doi.org/10.1109/LED.2013.2253752

    Article  CAS  Google Scholar 

  66. Goswami Y, Asthana P, Basak S, Ghosh B (2015) Junctionless tunnel field effect transistor with nonuniform doping. Int J Nanosci 14:1–7. https://doi.org/10.1142/S0219581X14500252

    Article  CAS  Google Scholar 

  67. Xie H, Liu H, Wang S et al (2020) Improvement of electrical performance in heterostructure junctionless TFET based on dual material gate. Appl Sci 10. https://doi.org/10.3390/app10010126

  68. Rahimian M, Fathipour M (2017) Improvement of electrical performance in junctionless nanowire TFET using hetero-gate-dielectric. Mater Sci Semicond Process 63:142–152. https://doi.org/10.1016/j.mssp.2016.12.011

    Article  CAS  Google Scholar 

  69. Singh B, Gola D, Goel E et al (2016) Dielectric pocket double gate junctionless FET: a new MOS structure with improved subthreshold characteristics for low power VLSI applications. J Comput Electron 15:502–507. https://doi.org/10.1007/s10825-016-0808-3

    Article  CAS  Google Scholar 

  70. Devi WV, Bhowmick B (2019) Optimisation of pocket doped junctionless TFET and its application in digital inverter. Micro Nano Lett 14:69–73. https://doi.org/10.1049/mnl.2018.5086

    Article  CAS  Google Scholar 

  71. Yao L, Liang R, Jiang C et al (2014) Investigation of the junctionless line tunnel field-effect transistor. 2014 Int Symp Next-Generation Electron ISNE. https://doi.org/10.1109/ISNE.2014.6839326

  72. Han T, Liu H, Wang S et al (2019) Design and investigation of the junction-less TFET with Ge/Si0.3Ge0.7/Si heterojunction and heterogeneous gate dielectric. Electron 8. https://doi.org/10.3390/electronics8050476

  73. Hemanjaneyulu K, Shrivastava M (2015) Fin enabled area scaled tunnel FET. IEEE Trans Electron Devices 62:3184–3191. https://doi.org/10.1109/TED.2015.2469678

    Article  CAS  Google Scholar 

  74. Chen S, Wang S, Liu H et al (2020) A Novel Dopingless Fin-Shaped SiGe Channel TFET with Improved Performance. Nanoscale Res Lett 15. https://doi.org/10.1186/s11671-020-03429-3

  75. Lee M-Y, Chiu CH, Hsieh ER et al (2021) Fin-TFET: Design of FinFET-based Tunneling FET with Face-tunneling Mechanism. Silicon Nanoelectronics Workshop (SNW): 1–2. https://doi.org/10.1109/SNW51795.2021.00009

  76. Kim JH, Kim HW, Kim G et al (2019) Demonstration of fin-tunnel field-effect transistor with elevated drain. Micromachines 10:1–10. https://doi.org/10.3390/mi10010030

    Article  Google Scholar 

  77. Lim D, Han H, Choi C (2019) Tunneling field effect transistors (TFETs) with 3D fin-shaped channel structure and their electrical characteristics. Solid State Electron 154:1–6. https://doi.org/10.1016/j.sse.2019.01.003

    Article  CAS  Google Scholar 

  78. Ravindran A, George A, Praveen CS, Kuruvilla N (2017) Gate all around nanowire TFET with high ON/OFF current ratio. Mater Today Proc 4:10637–10642. https://doi.org/10.1016/j.matpr.2017.06.434

    Article  Google Scholar 

  79. Singh A, Pandey CK (2022) Improved DC performances of gate-all-aroundSi-nanotube tunnel FETs using gate-source overlap. Silicon 14:1463–1470. https://doi.org/10.1007/s12633-021-00957-0

    Article  CAS  Google Scholar 

  80. Sahay S, Kumar MJ (2016) Insight into lateral band-to-band-tunneling in nanowire Junctionless FETs. IEEE Trans Electron Devices 63:4138–4142. https://doi.org/10.1109/TED.2016.2601239

    Article  CAS  Google Scholar 

  81. Vishnoi R, Kumar MJ (2014) Compact analytical drain current model of gate-all-around nanowire tunneling FET. IEEE Trans Electron Devices 61:2599–2603. https://doi.org/10.1109/TED.2014.2322762

    Article  Google Scholar 

  82. Vishnoi R, Kumar MJ (2014) A pseudo-2-D-analytical model of dual material gate all-around nanowire tunneling FET. IEEE Trans Electron Devices 61:2264–2270. https://doi.org/10.1109/TED.2014.2321977

    Article  Google Scholar 

  83. Vishnoi R, Kumar MJ (2015) A compact analytical model for the drain current of gate-all-around nanowire tunnel FET accurate from sub-threshold to ON-State. IEEE Trans Nanotechnol 14:358–362. https://doi.org/10.1109/TNANO.2015.2395879

    Article  CAS  Google Scholar 

  84. Anamul Haque A, Mishra V, Verma YK, Gupta SK (2022) Investigation of novel low bandgap source material for hetero-dielectric GAA-TFET with enhanced performance. Silicon. https://doi.org/10.1007/s12633-021-01571-w

  85. Musalgaonkar G, Sahay S, Saxena RS, Kumar MJ (2019) Nanotube tunneling FET with a core source for ultrasteep subthreshold swing: a simulation study. IEEE Trans Electron Devices 66:4425–4432. https://doi.org/10.1109/TED.2019.2933756

    Article  CAS  Google Scholar 

  86. Dash S, Mishra GP (2015) A new analytical threshold voltage model of cylindrical gate tunnel FET (CG-TFET). Superlattices Microstruct 86:211–220. https://doi.org/10.1016/j.spmi.2015.07.049

    Article  CAS  Google Scholar 

  87. Usha C, Vimala P (2021) An analytical modeling of conical gate-all-around tunnel field effect transistor. Silicon 13:2563–2568. https://doi.org/10.1007/s12633-020-00611-1

    Article  CAS  Google Scholar 

  88. G LP, N B B (2020) Improvement of subthreshold characteristics of dopingless tunnel FET using hetero gate dielectric material: analytical modeling and simulation. Silicon 12:2189–2201. https://doi.org/10.1007/s12633-019-00314-2

  89. Gedam A, Acharya B, Mishra GP (2021) Junctionless silicon nanotube TFET for improved DC and radio frequency performance. Silicon 13:167–178. https://doi.org/10.1007/s12633-020-00410-8

    Article  CAS  Google Scholar 

  90. Ajay, Narang R, Saxena M, Gupta M (2018)Two-dimensional(2D) analytical investigation of an n-type junctionless gate-all-around tunnel field-effect transistor (JL GAA TFET). J Comput Electron 17:713–723. https://doi.org/10.1007/s10825-018-1151-7

  91. Reddy NN, Panda DK (2021) Nanowire gate all around-TFET-based biosensor by considering ambipolar transport. Appl Phys A Mater Sci Process. https://doi.org/10.1007/s00339-021-04840-y

    Article  Google Scholar 

  92. Wighmal K, Peddi G, Apoorva et al (2021) Gate all around dopingless nanotube TFET biosensor with Si0.5Ge0.5 – Based source. Silicon. https://doi.org/10.1007/s12633-021-01361-4

  93. Priya GL, Venkatesh M, Balamurugan NB, Samuel TSA (2021) Triple metal surrounding gate junctionless tunnel FET based 6T SRAM design for low leakage memory system. Silicon 13:1691–1702. https://doi.org/10.1007/s12633-021-01075-7

    Article  CAS  Google Scholar 

Download references

Acknowledgements

The authors would like to thank National Institute of Technology, Warangal, Telangana, India, for providing necessary infrastructure to carry out this work.

Author information

Authors and Affiliations

Authors

Contributions

All authors have made substantial contributions in drafting the manuscript or revising it critically for important intellectual content.

Corresponding author

Correspondence to Ekta Goel.

Ethics declarations

The manuscript follows all the ethical standards, including plagiarism.

Consent for Publication

Yes.

Consent to Participate

Yes.

Conflict of Interest

No conflicts of interest.

Additional information

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Electronic Supplementary Material

Below is the link to the electronic supplementary material.

Supplementary Material 1

Supplementary Material 2

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Babu, K.M.C., Goel, E. Evolution of Tunnel Field Effect Transistor for Low Power and High Speed Applications: A Review. Silicon 14, 11051–11060 (2022). https://doi.org/10.1007/s12633-022-01826-0

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s12633-022-01826-0

Keywords

Navigation