Dynamic Crosstalk Analysis in Coupled Interconnects for Ultra-Low Power Applications

Abstract

Ultra-low power circuit design has received a wide attention due to the fast growth and prominence of portable battery-operated devices with stringent power constraint. Though sub-threshold circuit operation shows huge potential toward satisfying the ultra-low power requirement, it holds challenging design issues. Of these, the increased crosstalk and delay have become serious challenges, particularly for sub-threshold interconnects as integration density increases with every scaled technology node. Consequently, in this paper an analytical approach providing closed form expressions for dynamic crosstalk in coupled interconnects under sub-threshold condition has been proposed. The proposed model is based on the sub-threshold current–voltage expression for a metal-oxide semiconductor transistor. The model determines the propagation delay and timings of the aggressor and victim drivers for the conditions when inputs are switching in-phase and out-of-phase. Subsequently, the transient analysis of dynamic crosstalk is carried out. The comparison of analytical results with SPICE shows that the model captures waveform shape, propagation delay, and timing with good accuracy, with less than 5 % error in timing estimation.

Appendices

Appendix 1

1.1 Output Voltages for Slow Ramp Input Signal: In-Phase Switching

If the active device enters into sub-linear region before the completion of input transition, the input ramp signal is a slow ramp signal. The output voltages of coupled buffers in the time interval $0\le t\le \varsigma _{n_1 }$ are essentially similar to (8) and (9). At $\varsigma _{n_1 }$ instant, MN1 leaves the sub-saturation region. MN2 makes transition to sub-linear region of its characteristics at $t =\varsigma _{n_2 }$. The output voltages of each CMOS buffer in this interval are given by following expressions:

$$\begin{aligned} V_1&=V_{1_{{t}=\varsigma _{n_1 } } } \mathrm{e}^{-\alpha _{n_1 } ( {t-\varsigma _{n_1 } })}-\frac{C_\mathrm{c} B_{n_2 } {\tau }_\mathrm{r} {\eta }_n U_{\mathrm{th}} \mathrm{e}^{-\frac{V_{\mathrm{DD}} }{{\eta }_n U_{\mathrm{th}} }}}{V_{\mathrm{DD}} \left[ {C_1 C_2 +C_\mathrm{c} ( {C_1 +C_2 })} \right] +{\tau }_\mathrm{r} {\eta }_n U_{\mathrm{th}} ( {C_2 +C_\mathrm{c} })\gamma _{n_1 } }\nonumber \\&\quad \times \left[ {\mathrm{e}^{\frac{V_{\mathrm{DD}} ( {t-\varsigma _{n_1 } })}{{\tau }_\mathrm{r} {\eta }_\mathrm{n} U_{\mathrm{th}} }}-\mathrm{e}^{-\alpha _{n_1 } ( {t-\varsigma _{n_1 } })}} \right] \end{aligned}$$

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$$\begin{aligned} V_2&= V_{2_{t=\varsigma _{n_1 } } } - R_2 B_{n_2 } -\frac{B_{n_2 } {\tau }_\mathrm{r} {\eta }_n U_{\mathrm{th}} ( {C_1 +C_\mathrm{c} })}{V_{\mathrm{DD}} \left[ {C_1 C_2 +C_\mathrm{c} ( {C_1 +C_2 })} \right] }\mathrm{e}^{-\frac{V_{\mathrm{DD}} }{{\eta }_n U_{\mathrm{th}} }}\left[ {\mathrm{e}^{\frac{V_{\mathrm{DD}} }{{\tau }_\mathrm{r} }( {t-\varsigma _{n_1 } })}-1} \right] \nonumber \\&\quad -\frac{C_\mathrm{c} }{C_1 C_2 +C_\mathrm{c} ( {C_1 +C_2 })}\gamma _{n_1 } \int \limits _{\varsigma _{n_1 } }^{t} {V_1 } \mathrm{d}t. \end{aligned}$$

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Appendix 2

1.1 Output Voltages for Slow Ramp Input Signal: Out-of-Phase Switching

During the operating condition, $0\le t \le \varsigma _{\mathrm{p}_2 }$, expressions for the output voltages are same as for fast ramp input, i.e., (41) and (42). At $t=\varsigma _{p_2 }$, MP2 leaves the sub-saturation and enters into the sub-linear region. In the time limit $\varsigma _{p_2 } \le t \le \varsigma _{n_1 }$, the output voltages are given by

$$\begin{aligned} V_1&= V_{1_{{t}=\varsigma _{p_2 } } } - B_{n_1 } \left( {R_1 +\frac{( {C_2 +C_\mathrm{c} }) {\tau }_\mathrm{r} {\eta }_n U_{\mathrm{th}} }{( {C_1 C_2 + C_\mathrm{c} ( {C_1 + C_2 })})V_{\mathrm{DD}} }}\right) \left[ {\mathrm{e}^{\frac{\frac{V_{\mathrm{DD}} }{{\tau }_\mathrm{r} }( {t-\varsigma _{p_2 } })}{{\eta }_n U_{\mathrm{th}} }}- \mathrm{e}^{-\frac{V_{\mathrm{DD}} }{{\eta }_n U_{\mathrm{th}} }}} \right] \nonumber \\&\quad + \frac{C_\mathrm{c} }{C_1 C_2 +C_\mathrm{c} ( {C_1 + C_2 })}\gamma _{p_2 }\left[ {( {t-\varsigma _{p_2 } }) V_{\mathrm{DD}} -\int \limits _{\varsigma _{p_2 } }^{t} {V_2 } \mathrm{d}t} \right] \end{aligned}$$

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$$\begin{aligned} V_2&= V_{\mathrm{DD}} + \mathrm{e}^{-\alpha _{p_2 } ( {t-\varsigma _{p_2 } })}( {V_{2_{\mathrm{t}=\varsigma _{p_2 } } } -V_{\mathrm{DD}} })\nonumber \\&-\frac{C_\mathrm{c} B_{n_1 } {\tau }_\mathrm{r} {\eta }_n U_{\mathrm{th}} \mathrm{e}^{-\frac{V_{\mathrm{DD}} }{{\eta }_n U_{\mathrm{th}} }}\left[ {\mathrm{e}^{\frac{\frac{V_{\mathrm{DD}} }{{\tau }_\mathrm{r} }( {t-\varsigma _{p_2 } })}{{\eta }_n U_{\mathrm{th}} }}- \mathrm{e}^{-\alpha _{p_2 } ( {t-\varsigma _{\mathrm{p}_2 } })}} \right] }{V_{\mathrm{DD}} \left[ {C_1 C_2 +C_\mathrm{c} ( {C_1 + C_2 })} \right] +( {C_1 +C_\mathrm{c} })\gamma _{p_2 } {\tau }_\mathrm{r} {\eta }_n U_{\mathrm{th}} }\end{aligned}$$

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$$\begin{aligned}&\quad \mathrm{where}\,\,\alpha _{p_2 } =\frac{( {C_1 +C_\mathrm{c} })}{\left[ {C_1 C_2 +C_\mathrm{c} ( {C_1 +C_2 })} \right] (1+\gamma _{p_2 } R_2 )}\gamma _{p_2 }. \end{aligned}$$

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Appendix 3

1.1 Estimation of Interconnect Impedance Parasitics

The interconnect impedance parasitics, i.e., resistance and capacitance are presented here and are computed using Ref. [15]. Figure 9 shows the cross-sectional dimensions of interconnect where interconnect is assumed to be placed between two co-planar interconnects and two orthogonal routing planes.

Fig. 9

Interconnect cross-sectional dimensions

As shown in Fig. 9, if w and h are the width and the height of the interconnect, respectively, s is the separation between two interconnects, $t$ is the thickness of the dielectric, the interconnect resistance per unit length is given as,

$$\begin{aligned} R = \frac{\rho }{{wt}}, \end{aligned}$$

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where $\rho$ stands for the resistivity of the interconnect metal. The interconnect capacitance per unit length is calculated as

$$\begin{aligned} C = \varepsilon \left[ {\frac{{w}}{{h}}+2.22\left( {\frac{{s}}{{s}+0.70\mathrm{h}}}\right) ^{3.19}+1.17\left( {\frac{{s}}{{s}+1.51{h}}}\right) ^{0.76}\left( {\frac{t}{t+4.53{h}}}\right) ^{0.12}} \right] , \end{aligned}$$

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where $\varepsilon$ is the relative permittivity. It consists of the sum of three contributions from left to right: the ideal parallel-plate capacitor, the parallel-plate corner effects, and the sidewall capacitor. The interconnect coupling capacitance per unit length is determined using

$$\begin{aligned} C_{\mathrm{c}}&= \varepsilon \left[ 1.14\frac{t}{{s}} \left( {\frac{{h}}{{h}+2.06{s}}}\right) ^{0.09}+0.74 \left( {\frac{{w}}{{w}+1.59 {s}}}\right) ^{1.14}\right. \nonumber \\&\quad \left. +1.16 \left( {\frac{{w}}{{w}+1.87 {s}}}\right) ^{0.16}\left( {\frac{{h}}{{h}+0.98{s}}}\right) ^{1.18} \right] . \end{aligned}$$

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