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Dynamic X-filling for Peak Capture Power Reduction for Compact Test Sets

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Abstract

Excessive test power consumption is one of the obstacles which the chip industry currently faces. Peak capture power reduction typically leads to high pattern counts which increase test costs. This paper proposes a new methodology to reduce peak capture power during at-speed scan testing. In this method, a novel dynamic X-filling technique Opt-Justification-fill which uses optimization techniques to compute promising X-bits for low-power filling is proposed. This method is tightly integrated into a dynamic compaction flow to create silent test cubes with high compaction ability. By this, X-filling for fault detection and reducing switching activity is balanced. The proposed methodology can be applied during initial compact test set generation as well as during a post-ATPG stage for a previously generated test set to reduce switching activity. Experiments show a significant reduction of peak capture power. At the same time, the pattern count increase is only small which leads to reduced test costs.

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Notes

  1. This article is an extended version of an Asian Test Symposium paper [6]. More details and examples about the proposed methodology are included. Furthermore, the experimental section has been extended to include larger circuits as well as an evaluation of the iterative application.

  2. Recently, clasp won several awards for its performance in various categories of SAT solving in international SAT solver competitions.

References

  1. Butler KM, Saxena J, Jain A, Fryars T, Lewis J, Hetherington G (2004) Minimizing power consumption in scan testing: pattern generation and DFT techniques. In: International test conference, pp 355–364

  2. Chakravadhanula K, Chickermane V, Keller B, Gallagher P, Narang P (2009) Capture power reduction using clock gating aware test generation. In: International test conference, pp 1–9

  3. Corno F, Prinetto P, Rebaudengo M, Sonza-Reorda M (1998) A test pattern generation methodology for low power consumption. In: VLSI test symposium, pp 453–457

  4. Czutro A, Sauer M, Polian I, Becker B (2012) Multi-conditional SAT-ATPG for power-droop testing. In: IEEE European test symposium, pp 1–6

  5. Drechsler R, Eggersglüß S, Fey G, Glowatz A, Hapke F, Schloeffel J, Tille D (2008) On acceleration of SAT-based ATPG for industrial designs. IEEE Trans Comput-Aided Des Integ Circuits Syst 27(7):1329–1333

    Article  Google Scholar 

  6. Eggersglüß S (2013) Peak capture power reduction for compact test sets using opt-justification-fill. In: Proceedings of the IEEE Asian test symposium, pp 31–36

  7. Eggersglüß S, Wille R, Drechsler R (2013) Improved SAT-based ATPG: more constraints, better compaction. In: Proceedings of the international conference on computer-aided design, pp 85–90

  8. Eggersglüß S, Yilmaz M, Chakrabarty K (2012) Robust timing-aware test generation using pseudo-boolean optimization. In: Proceedings of the IEEE Asian test symposium, pp 290–295

  9. Enokimoto K, Wen X, Yamato Y, Miyase K, Sone H, Kajihara S, Aso M, Furukawa H (2009) CAT: a critical-area-targeted test set modification scheme for reducing launch switching activity in at-speed scan testing. In: IEEE Asian test symposium, pp 99–104

  10. Fang L, Hsiao MS (2008) A fast approximation algorithm for MIN-ONE SAT. In: Design, automation and test in Europe, pp 1087–1090

  11. Furukawa H, Wen X, Miyase K, Yamato Y, Kajihara S, Girard P, Wang LT, Tehranipoor M (2008) CTX: a clock-gating based test relaxation and X-filling scheme for reducing yield loss risk in at-speed scan testing. In: IEEE Asian test symposium, pp 397–402

  12. Gebser M, Kaufmann B, Neumann A, Schaub T (2007) Conflict-driven answer set solving. In: International joint conference on artificial intelligence, pp 386–392

  13. Girard P (2002) Survey of low-power testing of VLSI circuits. IEEE Des Test Comput 19(3):82–92

    Article  MathSciNet  Google Scholar 

  14. Girard P, Nicolici N, Wen X (eds) (2009) Power-aware testing and test strategies for low power devices. Springer

  15. Hamzaoglu I, Patel JH (1998) Test set compaction algorithms for combinational circuits. In: International conference on computer-aided design, pp 283–289

  16. Jiang Z, Wang Z, Wang LC, Walker DMH (2011) Levelized low cost delay test compaction considering IR-drop induced power supply noise. In: VLSI test symposium, pp 52–57

  17. Larrabee T (1992) Test pattern generation using Boolean satisfiability. IEEE Trans Comput-Aided Des Integ Circuits Syst 11(1):4–15

    Article  Google Scholar 

  18. Lee J, Tehranipoor M (2008) Layout-aware transition-delay fault pattern generation with evenly distributed switching activity. J Low Power Electron 4(3):1–12

    Article  Google Scholar 

  19. Lee J, Tehranipoor M (2008) LS-TDF: low-switching transition delay fault pattern generation. In: VLSI test symposium, pp 227–232

  20. Lee LJ (2013) Observation-oriented ATPG and scan chain disabling for capture power reduction. J Electron Testing: Theory Appl 29(5):625–634

    Article  Google Scholar 

  21. Li W, Reddy SM, Pomeranz I (2005) On reducing peak current and power during test. In: IEEE annual symposium on VLSI, pp 156–161

  22. Marques-Silva JP, Sakallah KA (1997) Robust search algorithms for test pattern generation. In: International symposium on fault-tolerant computing, pp 152–157

  23. Miyase K, Kajihara S (2004) XID: don’t care identification of test patterns for combinational circuits. IEEE Trans Comput-Aided Des Int Circuits Syst 23(2):321–326

    Article  Google Scholar 

  24. Moghaddam EK, Rajski J, Reddy SM, Kassab M (2010) At-speed scan test with low switching activity. In: VLSI test symposium, pp 177–182

  25. Remersaro S, Lin X, Reddy SM, Pomeranz I, Rajski J (2007) Scan-based tests with low switching activity. IEEE Des Test Comput 24(3):268–275

    Article  Google Scholar 

  26. Remersaro S, Lin X, Zhang Z, Reddy SM, Pomeranz I, Rajski J (2006) Preferred fill: a scalable method to reduce capture power for scan based designs. In: International test conference, pp 1–10

  27. Sauer M, Reimer S, Schubert T, Polian I, Becker B (2013) Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths. In: Design, automation and test in Europe, pp 448–453

  28. Saxena J, Butler KM, Jayaram VB, Kundu S, Arvind NV, Sreeprakash P, Hachinger M (2003) A case study of IR-drop in structured at-speed testing. In: International test conference, pp 1098–1104

  29. Sde-Paz S, Salomon E (2008) Frequency and power correlation between at-speed scan and functional tests. In: International test conference, pp 1–9

  30. Stephan P, Brayton RK, Sangiovanni-Vincentelli AL (1996) Combinational test generation using satisfiability. IEEE Trans Comput-Aided Des Int Circuits Syst 15(9):1167–1176

    Article  Google Scholar 

  31. Wang S, Gupta SK (2002) An automatic test pattern generator for minimizing switching activity during scan testing activity. IEEE Trans Comput-Aided Des Int Circuits Syst 21(8):954– 968

    Article  Google Scholar 

  32. Wen X, Enokimoto K, Miyase K, Yamato Y, Kochte MA, Kajihara S, Girard P, Tehranipoor M (2011) Power-aware test generation with guaranteed launch safety for at-speed scan testing. In: VLSI test symposium, pp 166–171

  33. Wen X, Kajihara S, Miyase K, Suzuki T, Saluja K, Wang LT, Abdel-Hafez K, Kinoshita K (2006) A new ATPG method for efficient capture power reduction during scan testing. In: VLSI test symposium, pps 58–65

  34. Wen X, Miyase K, Kajihara S, Suzuki T, Yamato Y, Girard P, Ohsumi Y, Wang LT (2007) A novel scheme to reduce power supply noise for high-quality at-speed scan testing. In: International test conference, pp 1–10

  35. Wen X, Miyase K, Suzuki T, Kajihara S, Ohsumi Y, Saluja KK (2007) Critical-path-aware X-filling for effective IR-drop reduction in at-speed scan testing. In: Design automation conference, pp 527–532

  36. Wen X, Miyase K, Suzuki T, Kajihara S, Wang LT, Saluja KK, Kinoshita K (2008) Low capture switching activity test generation for reducing IR-drop in at-speed scan testing. J Electron Test: Theory Appl 24(4):379–391

    Article  Google Scholar 

  37. Wen X, Nishida Y, Miyase K, Kajihara S, Girard P, Tehranipoor M, Wang LT (2012) On pinpoint capture power management in at-speed scan test generation. In: International test conference, pp 1–8

  38. Wu MF, Hu KS, Huang JL (2009) LPTest: a flexible low-power test pattern generator. J Electron Test: Theory Appl 25(6):323–335

    Article  Google Scholar 

  39. Zhang T, Walker DMH (2013) Power supply noise control in pseudo functional test. In: VLSI test symposium, pp 1–6

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Acknowledgment

This article has been supported by the Institutional Strategy of the University of Bremen, funded by the German Excellence Initiative.

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Authors and Affiliations

  1. Institute of Computer Science, University of Bremen, Bremen, Germany

    Stephan Eggersglüß

  2. German Research Center for Artificial Intelligence (DFKI) - Cyber-Physical Systems, Bremen, Germany

    Stephan Eggersglüß

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  1. Stephan Eggersglüß
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Correspondence to Stephan Eggersglüß.

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Responsible Editor: J.-L. Huang

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Eggersglüß, S. Dynamic X-filling for Peak Capture Power Reduction for Compact Test Sets. J Electron Test 30, 557–567 (2014). https://doi.org/10.1007/s10836-014-5472-6

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  • DOI: https://doi.org/10.1007/s10836-014-5472-6

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