Abstract
Eliminating the excessive test power for integrated circuits is a strict challenge within the nanometer era. This method combines test pattern generation with the scan chain disabling technique to achieve low capture power testing under the single stuck-at fault model. Testability analysis is exploited to assist in the test pattern generation process to generate the observation-oriented test patterns. In order to direct fault effects to the frequently-used circuit outputs, unbalanced observability costs are purposely assigned to circuit outputs to introduce unequal propagation probability. Observation-aware scan chain clustering is then performed through a weighted compatibility analysis to densely cluster the frequently-used scan cells into scan chains. Consequently, more scan chains can be disabled in the capture cycle and significant power reduction can be achieved without affecting the fault coverage. To simultaneously consider the reduction in large test data volume and capture power, the power-aware test vector compaction algorithm is also performed. Experimental results for the large ISCAS’89 benchmark circuits show that significant improvements can be simultaneously achieved including 71.7 % of capture power reduction, 43.7 % of total power reduction, 24.3 % of peak power reduction and 98.0 % of test data compaction ratios averagely. Results for three large ITC’99 benchmark circuits also demonstrate the effectiveness of the proposed method for the practical-scale circuits.
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Almukhaizim S, Sinanoglu O (2009) Dynamic scan chain partitioning for reducing peak shift power during test. IEEE Trans Comput-Aided Des Integr Circ Syst 28(2):298–302
Chakravadhanula K (2009) Capture power reduction using clock gating aware test generation. Proc Intl Test Conf:1–9
Chou R, Saluja K, Agrawal V (1997) Scheduling tests for VLSI systems under power constraints. IEEE Trans VLSI Syst 5(6):175–185
Czysz D, Kassab M, Lin X, Mrugalski G, Rajski J, Tyszer J (2008) Low power scan shift and capture in the EDT environment. Proc Intl Test Conf:1–10
Dabholkar V, Chakravarty S, Pomeranz I, Reddy S (1998) Techniques for minimizing power dissipation in scan and combinational circuits during test application. IEEE Trans Comput-Aided Des 17:1325–1333
Elm M, Wunderlich H-J, Imhof ME, Zoellin CG, Leenstra J, Maeding N (2008) Scan chain clustering for test power reduction. Proc. Design Automation Conference: 828–833
Gerstendorfer S, Wunderlich H J (1999) Minimized power consumption for scan-based BIST. Proc IEEE intl Test Conf:77–84
Girard P (2002) Survey of low-power testing of VLSI circuit. Proc IEEE VLSI Test Symp:82–92
Goldstein LH, Thigpen EL (1980) SCOAP: Sandia controllability/observability analysis program. Proc Design Automation conf: 190–196
Hamzaoglu I, Patel JH (2000) Test set compaction algorithms for combinational circuits. IEEE Trans Comput-Aided Design Integr Circuits Syst 19(8):957–963
Huang T, Lee K (2001) Reduction of power consumption in scan-based circuits during test application by an input control technique. IEEE Trans Comput-Aided Des 20:911–917
Jha NK, Gupta S (2003) Testing of digital systems. Cambridge University Press
Lee L-J, He C-C, Tseng W-D (2012) Deterministic ATPG for low capture power testing. Proc IEEE Intl Microprocessor Test and Verification: 24–29
Lee K-J, Hsu S-J, Ho C-M (2004) Test power reduction with multiple capture orders. Asian Test Symposium: 26–31
Lee L-J, Tseng W-D, Lin R-B (2008) Power reduction during scan testing based on multiple capture technique. IEICE Trans Electron E91-C(5):798–805
Li B, Fang L, Hsiao MS (2007) Efficient power droop aware delay fault testing. Proc Intl Test Conf: 1–10
Li W, Reddy SM, Pomeranz I (2004) On test generation for transition faults with minimized peak power dissipation. Proc Design Automation Conf:504–509
Lin C-Y, Lin H-C, Chen H-M (2010) On reducing test power and test volume by selective pattern compression schemes. IEEE Trans Very Large Scale Integr (VLSI) Syst 18(8):1220–1224
Liu C, Iyengar V, Pradhan D K (2006) Thermal-aware testing of network-on-chip using multiple clocking. Proc VLSI Test Symp:46–51
Mitra D, Bhattacharjee S, Sur-Kolay S, Bhattacharya BB, Zachariah ST, Kundu S (2006) Test pattern generation for power supply droop Faults. Proc Intl Conf on VLSI Design: 343–348
Nadeau-Dostie B, Takeshita K, Cote J-F (2008) Power-aware at-speed scan test methodology for circuits with synchronous clocks. Proc Intl Test Conf: 1–10
Polian I, Czutro A, Kundu S, Becker B (2007) Power droop testing. IEEE Des Test Comput 24(3):276–284
Ravikumar CP, Hirech M, Wen X (2008) Test strategies for low-power devices. Low Power Electron 4(2):127–138
Rosinger PM, Al-Hashimi BM, Nicolici N (2002) Scan architecture for shift and capture cycle power reduction. Proc Intl Symp on Defect and Fault Tolerance in VLSI System: 129–137
Sankaralingam R, Pouya B, Touba NA (2001) Reducing power dissipation during test using scan chain disable. Proc. VLSI Test Symp: 319–324
Sankaralingam R, Touba N (2002) Controlling peak power during scan testing. Proc VLSI Test Symp: 153–159
Saxena J, Butler K M, Whetsel L (2001) An analysis of power reduction techniques in scan testing. Proc Intl Test Conf:670–677
Sying-Jyan W, Yan-Ting C, Li K S-M (2007) Low capture power test generation for launch-off-capture transition test based on don’t-care filling. IEEE International Symposium on Circuits and Systems: 3683–3686
Tzeng C-W, Huang S-Y (2008) UMC-Scan test methodology: Exploiting the maximum freedom of multicasting. IEEE Des Test Comput 25(2):132–140
Wang S, Gupta S (1998) ATPG for heat dissipation minimization during test application. IEEE Trans Comput 47(2):256–262
Wen X (2008) CTX: A clock-gating-based test relaxation and X-filling scheme for reducing yield loss risk in at-speed scan testing. Proc Asian Test Symp:397–402
Wen X, Yamashita Y, Kajihara S, Wang L-T, Saluja KK, Kinoshita K (2005) On low-capture-power test generation for scan testing. VLSI Test Symposium: 265–270
Whetsel L (2000) Adapting scan architectures for low power operation. Proc IEEE intl Test Conf: 863–872
Zorian Y (1993) A distributed BIST control scheme for complex VLSI devices. Proc VLSI Test Symp: 4–9
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Lee, LJ. Observation-Oriented ATPG and Scan Chain Disabling for Capture Power Reduction. J Electron Test 29, 625–634 (2013). https://doi.org/10.1007/s10836-013-5404-x
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DOI: https://doi.org/10.1007/s10836-013-5404-x