Abstract
Testing is a mandatory process to ensure the competence of Integrated circuit design. Testability measure in sequential circuits is arduous so, to alleviate the testing process, scan design is implemented. Power consumption in digital circuits surge during the testing phase due to the application of enormous test patterns to meet fault coverage. This paper proposes a power minimization technique by modifying test patterns. State skip LFSR methodology is proposed to meet test pattern compaction and Prim’s algorithm to reorder compressed patterns. Prim’s algorithm focuses on reduction of switching activity by decreasing hamming distance among successive test patterns. The proposed methodology is implemented in ISCAS'89 benchmark circuits. Experimental results show an improvement of 72.72% in terms of switching activity with State skip LFSR conventional LFSR and 81.81% with Prim’s algorithm over conventional LFSR. Improvement in test data compression of 57.14% is observed with State skip LFSR over conventional LFSR.
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Asha Pon, S., Priya, S., Jeyalakshmi, V. (2023). Test Pattern Modification to Minimize Test Power in Sequential Circuit. In: Sharma, H., Saha, A.K., Prasad, M. (eds) Proceedings of International Conference on Intelligent Vision and Computing (ICIVC 2022). ICIVC 2022. Proceedings in Adaptation, Learning and Optimization, vol 17. Springer, Cham. https://doi.org/10.1007/978-3-031-31164-2_1
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DOI: https://doi.org/10.1007/978-3-031-31164-2_1
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