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Low-Power Scan Testing: A Scan Chain Partitioning and Scan Hold Based Technique

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Abstract

Power consumption during scan testing operations can be significantly higher than that expected in the normal functional mode of operation in the field. This may affect the reliability of the circuit under test (CUT) and/or invalidate the testing process increasing yield loss. In this paper, a scan chain partitioning technique and a scan hold mechanism are combined for low power scan operation. Substantial power reductions can be achieved, without any impact on the test application time or the fault coverage and without the need to use scan cell reordering or clock and data gating techniques. Furthermore, the proposed design solution for scan power alleviation, permits the efficient exploitation of X-filling techniques for capture power reduction or the use of extreme (power independent) compression techniques for test data volume reduction.

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Authors and Affiliations

  1. Department of Computer Science and Engineering, University of Ioannina, Ioannina, Greece

    Efi Arvaniti & Yiorgos Tsiatouhas

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  1. Efi Arvaniti
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  2. Yiorgos Tsiatouhas
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Correspondence to Yiorgos Tsiatouhas.

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Responsible Editor: P. Girard

This research has been co-funded by the European Union (European Social Fund) and Greek national resources under the framework of the “Thales” project of the “Education & Lifelong Learning” Operational Program.

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Arvaniti, E., Tsiatouhas, Y. Low-Power Scan Testing: A Scan Chain Partitioning and Scan Hold Based Technique. J Electron Test 30, 329–341 (2014). https://doi.org/10.1007/s10836-014-5453-9

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  • DOI: https://doi.org/10.1007/s10836-014-5453-9

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