Skip to main content
SpringerLink
Log in

Test Time Reduction in Automated Test Equipment (ATE)-Based Mechanism of Network-on-Chip Communication Infrastructure

  • Research Article - Computer Engineering and Computer Science
  • Published:
Arabian Journal for Science and Engineering Aims and scope Submit manuscript

Abstract

Network-on-chip (NoC) has been proposed as a scalable communication infrastructure to establish connections between integrated cores which are increased on a single chip. NoC structure consisting of components and elements such as routers, processing elements and links that can be error prone. Therefore, to achieve the correct functioning of a network, test operation has been a major concern for chip designers. In offline test mechanism, the distance between test pattern generator and destinations has significant impact on the test time. Using multicast scheme, this paper proposed a new mechanism that tests all cores. Our proposed approach first divides the network to four parts and then locates one ATE with four ports in the middle of the network. Based on our method, test operations are manipulated in parallel on each partition, individually. A new method is proposed that distributes test packets and collects test responses, simultaneously. Simulation results were also compared with some prior works by means of the proposed mechanism indicating that delivering test packets’ latency was decreased about 63% and the total number of hop counts to reach the specified destination was declined approximately 34%.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Benini L., Micheli G.D.: Networks on chips: a new SoC paradigm. IEEE Comput. 35, 70–78 (2002)

    Article  Google Scholar 

  2. Pande P.P., Grecu C., Jones M., Ivanov A., Saleh R.: Performance evaluation and design trade-offs for network on-chip interconnect architectures. IEEE Trans. Comput. 54(8), 1025–1040 (2005)

    Article  Google Scholar 

  3. Stensgaard, M.B.; Spars, J.: ReNoC: a network-on-chip architecture with reconfigurable topology. In: Second ACM/IEEE International Symposium on Networks-on-Chip, pp. 55–64 (2008)

  4. Amory, A.M.; Briao, E.; Cota, E.; Lubaszewski, M.; Moraes, F.G.: A scalable test strategy for network-on-chip routers. In: Proceedings of the IEEE International Test Conference, pp. 591–599 (2005)

  5. Cota E., Carro L., Lubaszewski M.: Reusing an on-chip network for the test of core-based systems. ACM Trans. Des. Autom. Electron. Syst. 9(4), 471–499 (2004)

    Article  Google Scholar 

  6. Cota E., Kastensmidt F.L., Cassel M., Herve M., Almeida P., Meirelles P., Amory A.M., Lubaszewski M.: A high-fault-coverage approach for the test of data, control, and handshake interconnects in mesh networks-on-chip. IEEE Trans. Computer. 57(9), 1202–1215 (2008)

    Article  MathSciNet  Google Scholar 

  7. Grecu C., Ivanov A., Saleh R., Pande P.P.: Testing network-on-chip communication fabrics. IEEE Trans. Comput. Aided Des. 26(12), 2201–2214 (2007)

    Article  Google Scholar 

  8. Zorian, Y.: Guest editor’s introduction: What is infrastructure IP? IEEE Des. Test Comput. 19, 3–5 (2002)

  9. Lee, J.D.; Mahapatra, R.N.: In-field NoC-based SoC testing with distributed test vector storage. In: IEEE International Conference on Computer Design (ICCD), pp. 206–211 (2008)

  10. Zheng, Y.; Wang, H.; Yang, S.; Jiang, C.; Gao, F.: Accelerating strategy for functional test of NoC communication fabric. In: Proceedings of the Test Symposium (ATS), pp. 224–227 (2010)

  11. Kakoee, M.R.; Bertacco, V.; Benini, L.: A distributed and topology-agnostic approach for on-line NoC testing. In: Proceedings of the Networks on Chip (NoCS), Fifth IEEE/ACM International Symposium on, Pittsburgh, PA, pp. 113–120 (2011)

  12. Cota E., Carro L., Lubaszewski M.: Reusing an on-chip network for the test of core-based systems. ACM Trans. Des. Autom. Electron. Syst. 9(4), 471–499 (2004)

    Article  Google Scholar 

  13. Cota E., Kastensmidt F.L., Cassel M., Herve M., Almeida P., Meirelles P., Amory A.M., Lubaszewski M.: A high-fault-coverage approach for the test of data, control, and handshake interconnects in mesh networks-on-chip. IEEE Trans. Comput. 57(9), 1202–1215 (2008)

    Article  MathSciNet  Google Scholar 

  14. Xiang, D.; Zhang, Y.: Cost-effective power-aware core testing in NoCs based on a new unicast-based multicast scheme. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30, 135–147 (2011)

  15. Cota E., Liu C.: Constraint-driven test scheduling for NoC-based systems. IEEE Trans. Comput. Aided Des. 25(11), 2465–2478 (2006)

    Article  Google Scholar 

  16. Dalmasso, J.; Cota, E.; Flottes, M.L.; Rouzeyre, B.: Improving the test of NoC-based SoCs with help of compression schemes. In: Proceedings of the Annual Symposium VLSI, pp. 139–144 (2008)

  17. McKinley P.K., Xu H., Hossein A.H., Ni L.M.: Unicast-based multicast communication in wormhole-routed networks. IEEE Trans. Parallel Distrib. Syst. 5(12), 1252–1265 (1994)

    Article  Google Scholar 

  18. Herve, M.; Almeida, P.; Kastensmidt, F.L.; Cota, E.; Lubaszewski, M.: Concurrent test of network-on-chip interconnects and routers. In: Proceedings of the IEEE Test Workshop, pp. 1–6 (2010)

  19. Xiang, D.; Liu, G.; Chakrabarty, K.; Fujiwara, H.: Thermal-aware test scheduling for NoC-based 3D integrated circuits. In: Proceedings of the 21th IFIP/IEEE International Conference on VLSI-SOC, pp. 96–101 (2013)

  20. Jerger, N.E.; Peh, L.S.: On-chip networks. Synth. Lectures Comput. Archit. (Morgan-Claypool Publishers) 4, 69–74 (2009)

  21. Dally,W.J.; Towles, B.: Principles and Practices of Interconnection Networks. The Morgan Kaufmann Series in Computer Architecture and Design, pp. 245–247. Elsevier, Amsterdam (2003)

  22. Duato, J.; Yalamanchili, S.; Lionel, L.: Interconnection Network. Published in Morgan Kaufmann, pp. 402–407 (2002)

  23. Xiang D., Hu D., Xu Q., Orailoglu A.: Low-power scan testing for test data compression using a routing-driven scan architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28, 1101–1105 (2009)

    Article  Google Scholar 

  24. Palesi, M.; Patti, D.; Fazzino, F.: Noxim: the NoC Simulator, User Guide. University of Catania. 2–4 (2005–2010). Accessed Jan 2013. http://www.noxim.org

Download references

Author information

Authors and Affiliations

  1. Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran

    Mona Soleymani & Midia Reshadi

Authors
  1. Mona Soleymani
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Midia Reshadi
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Mona Soleymani.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Soleymani, M., Reshadi, M. Test Time Reduction in Automated Test Equipment (ATE)-Based Mechanism of Network-on-Chip Communication Infrastructure. Arab J Sci Eng 40, 3197–3209 (2015). https://doi.org/10.1007/s13369-015-1803-x

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s13369-015-1803-x

Keywords

Search

Navigation