An approach for complete 2-D analytical potential modelling of fully depleted symmetric double gate junction less transistor

Abstract

A novel 2-D analytical potential model of source and drain region along with channel for a fully depleted symmetric double gate junction less transistor is presented in this paper. The boundary conditions for channel potential along the channel length is taken considering source and drain region and boundary conditions for source and drain potential model are derived from channel longitudinal potential expression. The potential model is validated using TCAD simulations. A method for scale length determination is also presented. Scale length expression is obtained from the transverse electrostatic potential expression. Scale length variation with silicon layer thickness and gate oxide thickness is shown. The dependence of Scale length on the dielectric constant is also shown for the three dielectrics—“$\hbox {SiO}_2$”, “$\hbox {Al}_2 \hbox {O}_3$” and “$\hbox {HfO}_2$”.

Appendix

This appendix shows how (5) can be obtained from (4).

At $y=\frac{t_{Si} }{2}$, from (4),

$$\begin{aligned}&\phi (x,y)=\phi _s =\phi _0 (x)+\frac{\in _{ox} }{t_{Si} \in _{Si} t_{ox} }(\phi _{gs} -\phi _s )\frac{t_{Si} }{4}^{2}\nonumber \\&\phi _s (1+\frac{\in _{ox} t_{Si} }{4\in _{Si} t_{ox} })=\phi _0 (x)+\frac{\in _{ox} t_{Si} }{4\in _{Si} t_{ox} }\phi _{gs}\nonumber \\&\phi _s (\frac{4\in _{Si} t_{ox} +\in _{ox} t_{Si} }{4\in _{Si} t_{ox} })=\phi _0 (x)+\frac{\in _{ox} t_{Si} }{4\in _{Si} t_{ox} }\phi _{gs}\nonumber \\&\hbox {Or, }\phi _s =\phi _0 (x)\frac{4\in _{Si} t_{ox} }{4\in _{Si} t_{ox} \!+\!\in _{ox} t_{Si} }+\frac{\in _{ox} t_{Si} }{4\in _{Si} t_{ox} +\in _{ox} t_{Si} }\phi _{gs}\nonumber \\ \end{aligned}$$

(15)

From (15) putting $\phi _s$ in (4),

$$\begin{aligned} \phi (x,y)=\phi _0 (x)+\frac{4\in _{ox} }{t_{Si} (4t_{ox} \in _{Si} +t_{Si} \in _{ox} )}\{\phi _{gs} -\phi _0 (x)\}y^{2} \end{aligned}$$