Introduction Takao NishitaniPeng H. AngFrancky Catthoor EditorialNotes 01 April 1993 Pages: 113 - 113
Single-chip image sensors with a digital processor array Robert ForchheimerKeping ChenAnders Ödmark OriginalPaper 01 April 1993 Pages: 121 - 131
An image processing system using Image Signal Multiprocessors (ISMPs) Hiroyuki NakahiraMasakatsu MaruyamaHaruyasu Yamada OriginalPaper 01 April 1993 Pages: 133 - 140
A video-rate JPEG chip set Peter A. RuetzPo TongPeng H. Ang OriginalPaper 01 April 1993 Pages: 141 - 150
DCT/IDCT processor for HDTV developed with dsp silicon compiler Takashi MiyazakiTakao NishitaniKaoru Mitsuhashi OriginalPaper 01 April 1993 Pages: 151 - 158
A VLSI based MIMD architecture of a multiprocessor system for real-time video processing applications Klaus GaedkeHartwig JeschkePeter Pirsch OriginalPaper 01 April 1993 Pages: 159 - 169
Design of a processing board for a programmable multi-VSP system M. EngelsR. LauwereinsA. van Roermund OriginalPaper 01 April 1993 Pages: 171 - 184
A VLSI neuroprocessor for image restoration using analog computing-based systolic architecture Ji-chien LeeBing J. SheuRama Chellappa OriginalPaper 01 April 1993 Pages: 185 - 199
Architectural strategies for high-throughput applications J. van MeerbergenP. LippensA. van Zanten OriginalPaper 01 April 1993 Pages: 201 - 220
An application-specific architecture for the RBN-coder with efficient memory organization Toon GijbelsFrancky CatthoorHugo de Man OriginalPaper 01 April 1993 Pages: 221 - 235
System considerations and the system level design of a chip set for real-time TV and HDTV motion estimation C. V. ReventlowM. TalmiC. Stoffers OriginalPaper 01 April 1993 Pages: 237 - 248
Systolic architectures for finite-state vector quantization Ravi K. KolagotlaShu-sun YuJoseph F. Jájá OriginalPaper 01 April 1993 Pages: 249 - 259
Parallel implementation for iterative image restoration algorithms on a parallel DSP machine Robert L. StevensonGeorge B. Adams IIIEdward J. Delp OriginalPaper 01 April 1993 Pages: 261 - 272
An optimization technique for lowering the iteration bound of DSP programs Frederico Buchholz MacielYoshikazu MiyanagaKoji Tochinai OriginalPaper 01 April 1993 Pages: 273 - 282