Abstract
We present a new systolic architecture for implementing Finite State Vector Quantization in real-time for both speech and image data. This architecture is modular and has a very simple control flow. Only one processor is needed for speech compression. A linear array of processors is used for image compression; the number of processors needed is independent of the size of the image. We also present a simple architecture for converting line-scanned image data into the format required by this systolic architecture. Image data is processed at a rate of 1 pixel per clock cycle. An implementation at 31.5 MHz can quantize 1024×1024 pixel images at 30 frames/sec in real-time. We describe a VLSI implementation of these processors.
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Kolagotla, R.K., Yu, Ss. & Jájá, J.F. Systolic architectures for finite-state vector quantization. J VLSI Sign Process Syst Sign Image Video Technol 5, 249–259 (1993). https://doi.org/10.1007/BF01581299
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DOI: https://doi.org/10.1007/BF01581299