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DCT/IDCT processor for HDTV developed with dsp silicon compiler

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Abstract

This article presents a discrete cosine transform (DCT) processor for high definition television (HDTV) by using an extended version of DSP Silicon Compiler. The extension is mainly concerned with module generation functions. A matrix-vector product module composed of multiply-accumulators (MACs) is newly added to the silicon compiler. The compiler accomplishes placement of leaf-cells and routing between the cells, referring to a prototype layout for the MAC. The prototype, which consists of a Booth multiplier and a carry look ahead adder, is carefully designed to attain high operation speed. The processor developed by the silicon compiler carries out 8×8 DCT and its inverse transform (IDCT). In order to evaluate the newly extended functions in the compiler, the architecture employed for the processor is based on the matrix-vector product method. By using DSP Silicon Compiler and 0.8 µm triple metal CMOS technology, the DCT processor is easily implemented with error-free environment and achieves a 50MHz data rate, which meets Japanese HDTV base line signal processing. The chip is implemented on a 12.80×12.57mm 2 area.

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Authors and Affiliations

  1. C&C Systems Research Laboratories, NEC Corporation, 4-1-1, Miyazaki, Miyamae-ku, 216, Kawasaki, Japan

    Takashi Miyazaki, Takao Nishitani, Masato Edahiro & Ikuko Ono

  2. R&D Planning and Technical Service Division, NEC Corporation, 4-1-1, Miyazaki, Miyamae-ku, 216, Kawasaki, Japan

    Kaoru Mitsuhashi

Authors
  1. Takashi Miyazaki
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  2. Takao Nishitani
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  3. Masato Edahiro
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  4. Ikuko Ono
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  5. Kaoru Mitsuhashi
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Miyazaki, T., Nishitani, T., Edahiro, M. et al. DCT/IDCT processor for HDTV developed with dsp silicon compiler. J VLSI Sign Process Syst Sign Image Video Technol 5, 151–158 (1993). https://doi.org/10.1007/BF01581292

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  • DOI: https://doi.org/10.1007/BF01581292

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