Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations S.J. SpinksC.D. ChalkM. Zwolinski OriginalPaper Pages: 11 - 23
Classification of Defective Analog Integrated Circuits Using Artificial Neural Networks V. StopjakováP. MalošekM. Margala OriginalPaper Pages: 25 - 37
Control and Observation Structure for Analog Circuits with Current Test Data Chun-Lung Hsu OriginalPaper Pages: 39 - 44
A Graph-Based Approach to Power-Constrained SOC Test Scheduling Chih-Pin SuCheng-Wen Wu OriginalPaper Pages: 45 - 60
Greedy Tree Growing Heuristics on Block-Test Scheduling Under Power Constraints Valentin MureşanXiaojun WangMircea Vlăduţiu OriginalPaper Pages: 61 - 78
A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques D. AppelloA. FudoliM. Sonza Reorda OriginalPaper Pages: 79 - 87
Testing and Reliability Techniques for High-Bandwidth Embedded RAMs Kanad Chakraborty OriginalPaper Pages: 89 - 108
Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor O. NovákZ. PlívaK. Gucwa OriginalPaper Pages: 109 - 122