1. Editorial

   • Vishwani D. Agrawal

   Legacy Pages: 167 - 167

2. New Editorial Board Members

   Legacy Pages: 169 - 170

3. An Implementation Approach of the IEEE 1149.1 for the Routing Test of a VLSI Massively Parallel Architecture

   • C. Aktouf
   • C. Robach
   • G. Mazare

   OriginalPaper Pages: 171 - 185

4. The Design and Implementation of an On-Line Testable UART

   • J. Yeandel
   • D. Thulborn
   • S. Jones

   OriginalPaper Pages: 187 - 198

5. Optimization of Mutual and Signature Testing Schemes for Highly Concurrent Systems

   • M.F. Abdulla
   • C.P. Ravikumar
   • Anshul Kumar

   OriginalPaper Pages: 199 - 216

6. Techniques for Reducing the Number of Decisions and Backtracks in Combinational Test Generation

   • Zohair Sahraoui
   • Francky Catthoor
   • Hugo de Man

   OriginalPaper Pages: 217 - 238

7. Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits

   • Lakshminarayana Pappu
   • Michael L. Bushnell
   • Srinivas Mandyam-Komar

   OriginalPaper Pages: 239 - 254

8. Combinatorial Analysis of Check Set Construction for Algorithm-Based Fault Tolerance Systems

   • De-Qiang Wang
   • Lian-Chang Zhao

   OriginalPaper Pages: 255 - 260