Abstract
Power dissipation has become a major concern in nanoscale integrated circuits. The power gating and dual-supply design methods are among the most effective approaches for reducing the static and dynamic power consumptions. However, these methods require efficient data retention and voltage level conversion. In this paper, a nonvolatile level converter flip-flop (NVLCFF) is proposed to be used in ultra-low-power integrated circuits. Our proposed NVLCFF employs the magnetic tunnel junction (MTJ) for data retention. Spin transfer torque along with the spin Hall effect is used for reconfiguring the MTJs. The peripheral circuitry is designed using 7-nm FinFET as one of the leading industrial technologies. Furthermore, to facilitate the use of the dual-supply approach, voltage level conversion is performed in the structure of the proposed NVLCFF. According to the HSPICE simulations, the power consumption, backup energy and restore energy of the proposed circuit are on average 59%, 48% and 92% lower than the other NVLCFFs based on the previous nonvolatile flip-flops with different MTJ structures. Furthermore, the comprehensive Monte Carlo simulations indicate the robustness of the proposed design in the presence of major MTJ and FinFET process variations as compared to the previous designs.
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M. Ahmadinejad, M.H. Moaiyeri, F. Sabetzadeh, Energy and area efficient imprecise compressors for approximate multiplication at nanoscale. AEU Int. J. Electron. Commun. 110, 1–11 (2019). https://doi.org/10.1016/j.aeue.2019.152859
S. Angizi, Z. He, A. Awad, D. Fan, MRIMA: an MRAM-based in-memory accelerator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2019). https://doi.org/10.1109/TCAD.2019.2907886
S. Angizi, Z. He, N. Bagherzadeh, D. Fan, Design and evaluation of a spintronic in-memory processing platform for nonvolatile data encryption. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(9), 1788–1801 (2017). https://doi.org/10.1109/TCAD.2017.2774291
L.T. Clark, V. Vashishtha, L. Shifren, A. Gujja, S. Sinha, B. Cline, C. Ramamurthy, G. Yeric, ASAP7: a 7-nm finFET predictive process design kit. Microelectron. J. 53, 105–115 (2016). https://doi.org/10.1016/j.mejo.2016.04.006
E. Deng, Y. Wang, Z. Wang, J.-O. Klein, B. Dieny, G. Prenat, W. Zhao, Robust magnetic full-adder with voltage sensing 2T/2MTJ cell, in Proceedings of 2015 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH´15). Boston, MA, pp 27–32 (2015). https://doi.org/10.1109/NANOARCH.2015.7180582
R. Dorrance, F. Ren, Y. Toriyama, A.A. Hafez, C.-K.K. Yang, D. Markovic, Scalability and design-space analysis of a 1 T-1 MTJ memory cell for STT-RAMs. IEEE Trans. Electron Devices 59(4), 878–887 (2012). https://doi.org/10.1109/TED.2011.2182053
X. Fong, R. Venkatesan, A. Raghunathan, K. Roy, Nonvolatile complementary polarizer spin-transfer torque on-chip caches: a device/circuit/systems perspective. IEEE Trans. Magn. (2014). https://doi.org/10.1109/TMAG.2014.2326858
S.K. Gupta, K. Roy, Low power robust FinFET-based SRAM design in scaled technologies, in Circuit Design for Reliability, ed. by R. Reis, Y. Cao, G. Wirth (Springer, New York, 2015), pp. 223–253. https://doi.org/10.1007/978-1-4614-4078-9_11
F. Ishihara, F. Sheikh, B. Nikolic, Level conversion for dual-supply systems. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 12(2), 185–195 (2004). https://doi.org/10.1109/TVLSI.2003.821548
A. Jaiswal, R. Andrawis, K. Roy, Area-efficient nonvolatile flip-flop based on spin Hall effect. IEEE Magn. Lett. 9, 1–4 (2018). https://doi.org/10.1109/LMAG.2018.2829676
M. Kazemi, E. Ipek, E.G. Friedman, Energy efficient nonvolatile flip flop with subnanosecond data backup time for fine grain power gating. IEEE Trans. Circuits Syst. II Express Briefs 62(12), 1154–1158 (2015). https://doi.org/10.1109/TCSII.2015.2468931
K.W. Kwon, S.H. Choday, Y. Kim, X. Fong, S.P. Park, K. Roy, SHE-NVFF: spin Hall effect based nonvolatile flip-flop for power gating architecture. IEEE Electron. Device Lett. 35(4), 488–490 (2014). https://doi.org/10.1109/LED.2014.2304683
M. Lanuzza, F. Crupi, S. Rao, R. De Rose, S. Strangio, G. Iannaccone, An ultra-low voltage energy efficient level shifter. IEEE Trans. Circuits Syst. II Express Briefs 64(1), 61–65 (2017). https://doi.org/10.1109/TCSII.2016.2538724
E. Maghsoudloo, M. Rezaei, M. Sawan, B. Gosselin, A high-speed and ultra low-power subthreshold signal level shifter. IEEE Trans. Circuits Syst. I Regul. Pap. 64(5), 1164–1172 (2017). https://doi.org/10.1109/TCSI.2016.2633430
M.H. Moaiyeri, R. Chavoshisani, A. Jalali, K. Navi, O. Hashemipour, High-performance mixed-mode universal min-max circuits for nanotechnology. Circuits Syst. Signal Process. 31(2), 465–488 (2012). https://doi.org/10.1007/s00034-011-9344-3
M. Moghaddam, M.H. Moaiyeri, M. Eshghi, A. Jalali, A low-power multiplier using an efficient single-supply voltage level converter. J. Circuits Syst. Comput. 24(8), 1550124 (2015). https://doi.org/10.1142/S0218126615501248
M. Moghaddam, S. Timarchi, M.H. Moaiyeri, M. Eshghi, An ultra-low-power 9T SRAM cell based on threshold voltage techniques. Circuits Syst Signal Process 35(5), 1437–1455 (2016). https://doi.org/10.1007/s00034-015-0119-0
R. Rajaei, A. Gholipour, Low power, reliable, and nonvolatile MSRAM cell for facilitating power gating and nonvolatile dynamically reconfiguration. IEEE Trans. Nanotechnol. 17(2), 261–267 (2018). https://doi.org/10.1109/TNANO.2018.2792782
F. Razi, M.H. Moaiyeri, R. Rajaei, S. Mohammadi, A variation-aware ternary spin-hall assisted STT-RAM based on Hybrid MTJ/GAA-CNTFET logic. IEEE Trans. Nanotechnol. 18(1), 598–605 (2019). https://doi.org/10.1109/TNANO.2019.2918198
M. Rostami, K. Mohanram, Dual-Vth independent-gate FinFETs for low power logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(3), 337–349 (2011). https://doi.org/10.1109/TCAD.2010.2097310
F. Sabetzadeh, M.H. Moaiyeri, M. Ahmadinejad, A majority-based imprecise multiplier for ultra-efficient approximate image multiplication. IEEE Trans. Circuits Syst. I Regul. Pap. 66(11), 4200–4208 (2019). https://doi.org/10.1109/TCSI.2019.2918241
S. Sayyah Ensan, M.H. Moaiyeri, B. Ebrahimi, S. Hessabi, A. Afzali-Kusha, A low-leakage and high-writable SRAM cell with back-gate biasing in FinFET technology. J. Comput. Electron. 18(2), 519–526 (2019). https://doi.org/10.1007/s10825-019-01327-1
S. Sayyah Ensan, M.H. Moaiyeri, M. Moghaddam, S. Hessabi, A low-power single-ended SRAM in FinFET technology. AEU Int. J. Electron. Commun. 99, 361–368 (2019). https://doi.org/10.1016/j.aeue.2018.12.015
Y. Seo, X. Fong, K. Roy, Fast and disturb-free nonvolatile flip-flop using complementary polarizer MTJ. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25(4), 1573–1577 (2017). https://doi.org/10.1109/TVLSI.2016.2631981
A. Shafaei, Y. Wang, M. Pedram, Low write-energy STT-MRAMs using FinFET-based access transistors, in 2014 IEEE 32nd International Conference on Computer Design (ICCD). 19–22 Oct. 2014, pp. 374–379. https://doi.org/10.1109/ICCD.2014.6974708
A. Shapiro, E.G. Friedman, Power efficient level shifter for 16 nm FinFET near threshold circuits. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 24(2), 774–778 (2016). https://doi.org/10.1109/TVLSI.2015.2409051
S. Shirinabadi Farahani, M.R. Reshadinezhad, A new twelve-transistor approximate 4:2 compressor in CNTFET technology. Int. J. Electron. 106(5), 691–706 (2019). https://doi.org/10.1080/00207217.2018.1545930
S. Sinha S, B. Cline, G. Yeric, V. Chandra, Y. Cao, Design benchmarking to 7 nm with FinFET predictive technology models, in 2012 ACM/IEEE International Symposium on Low Power Electronics and Design. 30 Jul–01 Aug. 2012, pp. 15–20. https://doi.org/10.1145/2333660.2333666
H. Taheri Tari, A. Dabaghi Zarandi, M. Reza Reshadinezhad, Design of a high performance CNTFET-based full adder cell applicable in: carry ripple, carry select and carry skip adders. Microelectron. Eng. 215, 110980 (2019). https://doi.org/10.1016/j.mee.2019.110980
A. Udhayakumar, S. Padma, Low power magnetic non-volatile flip-flops with self-time logical writing for high-end processors. Circuits Syst. Signal Process. 38(11), 4921–4932 (2019). https://doi.org/10.1007/s00034-019-01108-y
Z. Wang, W. Zhao, E. Deng, J.O. Klein, C. Chappert, Perpendicular-anisotropy magnetic tunnel junction switched by Spin-Hall-assisted spin-transfer torque. J. Phys. D Appl. Phys. (2015). https://doi.org/10.1088/0022-3727/48/6/065001
Z. Wang, W. Zhao, E. Deng, Y. Zhang, J.O. Klien, Magnetic non-volatile flip-flop with spin-Hall assistance. Phys Status Solidi (RRL) Rapid Res Let. 9(6), 375–378 (2015). https://doi.org/10.1002/pssr.201510097
C. Xu, Y. Zheng, D. Niu, X. Zhu, S.H. Kang, Y. Xie, Impact of write pulse and process variation on 22 nm FinFET-based STT-RAM design: a device-architecture co-optimization approach. IEEE Trans. Multi-Scale Comput. Syst. 1(4), 195–206 (2015). https://doi.org/10.1109/TMSCS.2015.2509960
Y. Zhang, W. Zhao, Y. Lakys, J.O. Klein, J.V. Kim, D. Ravelosona, C. Chappert, Compact modeling of perpendicular-anisotropy CoFeB/MgO magnetic tunnel junctions. IEEE Trans. Electron Devices 59(3), 819–826 (2012). https://doi.org/10.1109/TED.2011.2178416
Y. Zhang, X. Wang, Y. Chen, STT-RAM cell design optimization for persistent and non persistent error rate reduction: a statistical design view, in Proceedings of the International Conference on Computer-Aided Design. San Jose, CA, pp. 471–477 (2011). https://doi.org/10.1109/ICCAD.2011.6105370
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Morsali, M., Moaiyeri, M.H. NVLCFF: An Energy-Efficient Magnetic Nonvolatile Level Converter Flip-Flop for Ultra-Low-Power Design. Circuits Syst Signal Process 39, 2841–2859 (2020). https://doi.org/10.1007/s00034-019-01309-5
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DOI: https://doi.org/10.1007/s00034-019-01309-5