Low Power Magnetic Non-volatile Flip-Flops with Self-Time Logical Writing for High-End Processors

Abstract

Presently, leakage in a complementary metal oxide semiconductor (CMOS) increases due to high static power dissipation during reading and writing operations. Spin transfer torque magnetic random access memory is seen as the most reassuring non-volatile memory structure to overcome the current problem of static power dissipation. In conventional techniques, magnetic flip-flop (MFF) consumes large power and static current dissipation due to conditional-based single circuitry, which can be optimized through introduction of MFF with the combination of low swing conditional capture edge-trigged flip-flop, self-time logical writing circuit, and coarse-grain-based power gating circuit. This method has been developed particularly for high-precision, high-speed, mixed-mode application-specific integrated circuits; the reduction in total power consumption, static current, and PDP shows the proposed technique that as highly suitable for low power applications in high-end processors, using nanoscale technology. In this research work, results have been validated by simulations and measurements using 180 nm CMOS technology, tested using 1.8 v supply voltage.