Skip to main content
SpringerLink
Log in

Design an energy efficient pulse triggered ternary flip flops with Pseudo NCFET logic

  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

In electronic systems, flip-flops (FFs) are one of the fundamental elements that are used in high-performance processors. With the scaling of CMOS, occurs serious challenges such as higher leakage currents and higher static power consumption have been raised in high-performance circuits. Therefore, to address these issues, we explored carbon nanotube field effect transistors (CNTFETs) with multi-valued logic (MVL). In this paper, we designed an energy-efficient Pulse triggered Ternary Flip Flops (P-TFF) such as Data Close to Output (P-DCO-TFF), Signal Feed Through (P-SFT-TFF), and Delay (P-D-TFF) with pseudo NCFET (N-channel CNTFET) logic. These flip-flops use ternary logic, which is 0, Vdd/2, and Vdd as logic 0, 1, and 2, respectively. The complete design is done by the stanford 32 nm CNTFETs. The simulations are performed and waveforms are obtained in Cadence Virtuoso Software. We found that the suggested pulse-triggered TFFs performed better than the conventional ternary FF (C-TFF) structure in terms of energy, delay, and power. This simulation result shows 17.8%, 14%, and 47.7% energy reduction in P-SFT-TFF, P-DCO-TFF, and P-D-TFF, respectively, compared with C-TFF structure. Also performed the Monte Carlo Simulations to these proposed TFF designs. The P-D-TFF exhibits very efficient results in terms of delay, energy, and power consumption. This article also simulated the Ternary Universal Shift Register (TUSR) with Proposed P-D-TFF.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13

Similar content being viewed by others

Data availability

In this work, we used the Stanford university CNTFET 32 nm models for simulation. The models are openly available in [Stanford CNFET Model, Stanford Nanoelectronics Lab] at https://nano.stanford.edu/downloads/stanford-cnfet-model/stanford-cnfet-model-verilog [Ref 43]. We do not generate any datasets, because our work proceeds within a simulation approach. So, we provided the comparisons of simulation results in (Table 3) with [ref 34] [https://doi.org/10.1007/s10825-020-01516-3], [45] [https://doi.org/10.1016/j.aeue.2019.07.008], [46] [https://doi.org/10.1109/ICAIS53314.2022.9743096].

References

  1. Karimi, A., & Rezai, A. (2017). A design methodology to optimize the device performance in CNTFET. ECS Journal of Solid State Science and Technology, 6(8), M97–M102.

    Google Scholar 

  2. Amirany, A., Moaiyeri, M.H. and Jafari, K., (2020), January. Bio-inspired non-volatile and low-cost spin-based 2-Bit per cell memory. In 2020 25th international computer conference, computer society of Iran (CSICC) (pp. 1–7). IEEE.

  3. Kim, Y. B. (2010). Challenges for nanoscale MOSFETs and emerging nanoelectronics. Transactions on Electrical and Electronic Materials, 11(3), 93–105.

    Google Scholar 

  4. Basu, S., Bryant, R. E., De Micheli, G., Theis, T., & Whitman, L. (2018). Nonsilicon, non-von Neumann computing—Part I [scanning the issue]. Proceedings of the IEEE, 107(1), 11–18.

    Google Scholar 

  5. Deng, J. (2007) Device modeling and circuit performance evaluation for nanoscale devices: silicon technology beyond 45 nm node and carbon nanotube field effect transistors (Doctoral dissertation, Stanford University).

  6. Amirany, A. and Rajaei, R. (2018) Low power, and highly reliable single event upset immune latch for nanoscale CMOS technologies. In Electrical Engineering (ICEE), Iranian Conference on (pp. 103–107). IEEE.

  7. Weste, N. H., & Harris, D. (2010). Circuit design of latches and flip-flops in CMOS VLSI Design: A circuits and systems perspective (4th ed., pp. 392–402). Addison-Wesley.

    Google Scholar 

  8. Kaul, H., Anders, M., Hsu, S., Agarwal, A., Krishnamurthy, R. and Borkar, S. (2012) Near-threshold voltage (NTV) design: Opportunities and challenges. In Proceedings of the 49th Annual design automation conference (pp. 1153–1158).

  9. Jeon, D., Seok, M., Chakrabarti, C., Blaauw, D., & Sylvester, D. (2011). A super-pipelined energy efficient subthreshold 240 MS/s FFT core in 65 nm CMOS. IEEE Journal of Solid-State Circuits, 47(1), 23–34.

    Google Scholar 

  10. Jeong, H., Oh, T. W., Song, S. C., & Jung, S. O. (2018). Sense-amplifier-based flip-flop with transition completion detection for low-voltage operation. IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, 26(4), 609–620.

    Google Scholar 

  11. Chen, K. (2011) A 77% energy saving 22-transistor single phase clocking D flipflop with adoptive-coupling configuration in 40 nm CMOS. In Proceedings of the IEEE International Solid-State Circuits Conference (pp. 338–339)

  12. Moaiyeri, M. H., Jooq, M. K. Q., Al-Shidaifat, A., & Song, H. (2021). Breaking the limits in ternary logic: An ultra-efficient auto-backup/restore nonvolatile ternary flip-flop using negative capacitance CNTFET technology. IEEE Access, 9, 132641–132651.

    Google Scholar 

  13. Banerjee, A., Prasad, V., & Das, D. (2019). Design and analysis of ternary D-latch using CNTFETs. Journal of Nano-and Electronic Physics, 11(4), 04011–1.

    Google Scholar 

  14. Consoli, E., Palumbo, G., Rabaey, J. M., & Alioto, M. (2013). Novel class of energy-efficient very high-speed conditional push–pull pulsed latches. IEEE Transactions on Very Large Scale Integration VLSI Systems, 22(7), 1593–1605.

    Google Scholar 

  15. Karimi, A., Rezai, A., & Hajhashemkhani, M. M. (2017). A novel design for ultra-low power pulse-triggered D-flip-flop with optimized leakage power. Integration, 60(1), 160–166.

    Google Scholar 

  16. Hwang, Y. T., Lin, J. F., & Sheu, M. H. (2011). Low-power pulse-triggered flip-flop design with conditional pulse-enhancement scheme. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(2), 361–366.

    Google Scholar 

  17. Lin, J. F. (2013). Low-power pulse-triggered flip-flop design based on a signal feed-through. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22(1), 181–185.

    Google Scholar 

  18. Alioto, M., Consoli, E., & Palumbo, G. (2009). General strategies to design nanometer flip-flops in the energy-delay space. IEEE Transactions on Circuits and Systems I: Regular Papers, 57(7), 1583–1596.

    MathSciNet  Google Scholar 

  19. Rasouli, S. H., Khademzadeh, A., Afzali-Kusha, A., & Nourani, M. (2005). Low-power single-and double-edge-triggered flip-flops for high-speed applications. IEE Proceedings-Circuits, Devices and Systems, 152(2), 118–122.

    Google Scholar 

  20. Taghipour, S., & Asli, R. N. (2017). Aging comparative analysis of high-performance FinFET and CMOS flip-flops. Microelectronics Reliability, 69, 52–59.

    Google Scholar 

  21. Ghelichkhan, M., Hosseini, S. A., & Pishgar Komleh, S. H. (2020). Multi-digit binary-to-quaternary and quaternary-to-binary converters and their applications in nanoelectronics. Circuits, Systems, and Signal Processing, 39(4), 1920–1942.

    Google Scholar 

  22. Amirany, A., Jafari, K., & Moaiyeri, M. H. (2021). High-performance spintronic nonvolatile ternary flip-flop and universal shift register. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 29(5), 916–924.

    Google Scholar 

  23. Shou, X., Kalantari, N., & Green, M. M. (2006). Design of CMOS ternary latches. IEEE Transactions on Circuits and Systems I: Regular Papers, 53(12), 2588–2594.

    Google Scholar 

  24. Razi, F., Moaiyeri, M. H., Rajaei, R., & Mohammadi, S. (2019). A variation-aware ternary spin-Hall assisted STT-RAM based on hybrid MTJ/GAA-CNTFET logic. IEEE Transactions on Nanotechnology, 18, 598–605.

    Google Scholar 

  25. Doostaregan, A., & Abrishamifar, A. (2019). A new method for design of CNFET-based quaternary circuits. Circuits, Systems, and Signal Processing, 38(6), 2588–2606.

    Google Scholar 

  26. Kim, S., Lee, S. Y., Park, S., Kim, K. R., & Kang, S. (2020). A logic synthesis methodology for low-power ternary logic circuits. IEEE Transactions on Circuits and Systems I: Regular Papers, 67(9), 3138–3151.

    Google Scholar 

  27. Deng, J., & Wong, H. S. P. (2007). A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—Part I: Model of the intrinsic channel region. IEEE Transactions on Electron Devices, 54(12), 3186–3194.

    Google Scholar 

  28. Lee, C. S., Pop, E., Franklin, A. D., Haensch, W., & Wong, H. S. (2015). A compact virtual-source model for carbon nanotube FETs in the sub-10-nm regime—Part I: Intrinsic elements. IEEE Transactions on Electron Devices, 62(9), 3061–3069.

    Google Scholar 

  29. Lee, C. S., Pop, E., Franklin, A. D., Haensch, W., & Wong, H. S. P. (2015). A compact virtual-source model for carbon nanotube FETs in the sub-10-nm regime—Part II: Extrinsic elements, performance assessment, and design optimization. IEEE Transactions on Electron Devices, 62(9), 3070–3078.

    Google Scholar 

  30. McEuen, P. L., Fuhrer, M., & Park, H. (2002). Single-walled carbon nanotube electronics. IEEE Transactions on Nanotechnology, 1(1), 78–85.

    Google Scholar 

  31. Khezeli, M. R., Moaiyeri, M. H., & Jalali, A. (2018). Active shielding of MWCNT bundle interconnects: An efficient approach to cancellation of crosstalk-induced functional failures in ternary logic. IEEE Transactions on Electromagnetic Compatibility, 61(1), 100–110.

    Google Scholar 

  32. Jooq, M. K. Q., Bozorgmehr, A., & Mirzakuchaki, S. (2020). A low power and energy efficient 4: 2 precise compressor based on novel 14T hybrid full adders in 10 nm wrap gate CNTFET technology. Microelectronics Journal, 104, 104892.

    Google Scholar 

  33. Jooq, M. K. Q., Behbahani, F., & Moaiyeri, M. H. (2021). An ultra-efficient recycling folded cascode OTA based on GAA-CNTFET technology for MEMS/NEMS capacitive readout applications. AEU-International Journal of Electronics and Communications, 136, 153773.

    Google Scholar 

  34. Javadi, A. A., Morsali, M., & Moaiyeri, M. H. (2020). Magnetic nonvolatile flip-flops with spin-Hall assistance for power gating in ternary systems. Journal of Computational Electronics, 19(3), 1175–1186.

    Google Scholar 

  35. Jooq, M. K. Q., Bozorgmehr, A., & Mirzakuchaki, S. (2021). An ultra-miniature broadband operational transconductance amplifier utilizing 10 nm wrap-gate CNTFET technology. Analog Integrated Circuits and Signal Processing, 107(2), 423–434.

    Google Scholar 

  36. Wei, B. Q., Vajtai, R., & Ajayan, P. M. (2001). Reliability and current carrying capability of carbon nanotubes. Applied Physics Letters, 79, 1172–1174.

    Google Scholar 

  37. Karimi, A., Rezai, A., & Hajhashemkhani, M. M. (2019). Ultra-low power pulse-triggered CNTFET-based flip-flop. IEEE Transactions on Nanotechnology, 18, 756–761.

    Google Scholar 

  38. Liang, J., Chen, L., Han, J., & Lombardi, F. (2014). Design and evaluation of multiple valued logic gates using pseudo N-type carbon nanotube FETs. IEEE Transactions on Nanotechnology, 13(4), 695–708.

    Google Scholar 

  39. Patcha, K., Musala, S., Vijayavardhan, K., Sudha Vani, Y., & Srinivasulu, A. (2016). Carbon nano tube field effect transistors based ternary Ex-OR and Ex-NOR gates. Current Nanoscience, 12(4), 520–526.

    Google Scholar 

  40. Smith, K. C. (1981). The prospects for multivalued logic: A technology and applications view. IEEE Transactions on Computers, 30(09), 619–634.

    MathSciNet  Google Scholar 

  41. Appenzeller, J. (2008). Carbon nanotubes for high-performance electronics—Progress and prospect. Proceedings of the IEEE, 96(2), 201–211.

    Google Scholar 

  42. Doostaregan, A., & Abrishamifar, A. (2019). A new method for design of CNFET-based quaternary circuits. Circuits Systems and Signal Processing, 38(6), 2588–2606.

    Google Scholar 

  43. Razavi, S.E., Royaei, J. and Bahadorzadeh, M. (2015) Design a low current and high speed shift register based on d type flip flop. In 2015 Forth International conference on e-technologies and networks for development (ICeND) (pp. 1–4). IEEE.

  44. Hills, G., Lau, C., Wright, A., Fuller, S., Bishop, M. D., Srimani, T., Kanhaiya, P., Ho, R., Amer, A., Stein, Y., & Murphy, D. (2019). Modern microprocessor built from complementary carbon nanotube transistors. Nature, 572(7771), 595–602.

    Google Scholar 

  45. Rahbari, K., & Hosseini, S. A. (2019). Novel ternary d-flip-flap-flop and counter based on successor and predecessor in nanotechnology. AEU -International Journal of Electronics and Communications, 109, 107–120.

    Google Scholar 

  46. Sharma, T., Sharma, D. (2022) Design of ternary flip-flop cells using Maximum/Minimum logic operators in carbon nanotube technology. In 2022 Second International Conference on Artificial Intelligence and Smart Energy (ICAIS) (pp. 1693–1697).

  47. Bishop, D., et al. (2020). Fabrication of carbon nanotube field-effect transistors in commercial silicon manufacturing facilities. Nature Electronics, 3(8), 492–501.

    Google Scholar 

  48. Stanford CNFET Model, Stanford Nanoelectronics Lab, accessed 4th April 2019. https://nano.stanford.edu/downloads/stanford-cnfet-model/stanford-cnfet-model-verilog.

  49. Lin, A., Patil, N., Ryu, K., Badmaev, A., De Arco, L. G., Zhou, C., Mitra, S., & Wong, H. S. P. (2008). Threshold voltage and on–off ratio tuning for multiple-tube carbon nanotube FETs. IEEE Transactions on Nanotechnology, 8(1), 4–9.

    Google Scholar 

Download references

Funding

No funding is available for this publication.

Author information

Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Raghu Engineering College, Dakamari, Visakhapatnam, Andhra Pradesh, 531162, India

    Sudha Vani Yamani, Gundala Dinesh, Eegala Yamini Yeshaswila, Chelluri Ravi Teja & Botta Lokesh

  2. Department of Electronics and Communication, GITAM (Deemed to be University), Visakhapatnam, Andhra Pradesh, 530045, India

    M. V. S. RamPrasad

Authors
  1. Sudha Vani Yamani
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. M. V. S. RamPrasad
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Gundala Dinesh
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Eegala Yamini Yeshaswila
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Chelluri Ravi Teja
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. Botta Lokesh
    View author publications

    You can also search for this author in PubMed Google Scholar

Contributions

Dr. YSV and MVSRP concepts, Proof read, helped in Implementations, and written paper, GD, EYY, CRT and BL: concepts implementation and calculations.

Corresponding author

Correspondence to Sudha Vani Yamani.

Ethics declarations

Conflict of interest

The authors declare that they have no conflict of interest.

Ethical approval

Paper is plagiarism free.

Consent to participate

All authors given consents for the publication of this material.

Consent for publication

All authors given consents for the publication of this material.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Yamani, S.V., RamPrasad, M.V.S., Dinesh, G. et al. Design an energy efficient pulse triggered ternary flip flops with Pseudo NCFET logic. Analog Integr Circ Sig Process 119, 151–163 (2024). https://doi.org/10.1007/s10470-023-02236-x

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10470-023-02236-x

Keywords

Search

Navigation