Abstract
We report on the design and formal verification of a complex processor supporting address translation by means of a memory management unit (MMU). We give a paper and pencil proof that such a processor together with an appropriate page fault handler simulates virtual machines modeling user computation. These results are crucial steps towards the seamless verification of entire computer systems.
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Dalinger, I., Hillebrand, M., Paul, W. (2005). On the Verification of Memory Management Mechanisms. In: Borrione, D., Paul, W. (eds) Correct Hardware Design and Verification Methods. CHARME 2005. Lecture Notes in Computer Science, vol 3725. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11560548_23
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DOI: https://doi.org/10.1007/11560548_23
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-29105-3
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