Abstract
We describe a framework for verifying a pipelined microprocessor whose implementation contains precise exceptions, external interrupts, and speculative execution. We present our correctness criterion which compares the state transitions of pipelined and non-pipelined machines in presence of external interrupts. To perform the verification, we created a table-based model of pipeline execution. This model records committed and in-flight instructions as performed by the microarchitecture. Given that certain requirements are met by this table-based model, we have mechanically verified our correctness criterion using the ACL2 theorem prover.
This research was supported in part by the Semiconductor Research Corporation under contract 97-DJ-388.
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© 1998 Springer-Verlag Berlin Heidelberg
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Sawada, J., Hunt, W.A. (1998). Processor verification with precise exceptions and speculative execution. In: Hu, A.J., Vardi, M.Y. (eds) Computer Aided Verification. CAV 1998. Lecture Notes in Computer Science, vol 1427. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0028740
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DOI: https://doi.org/10.1007/BFb0028740
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