Overview
- Consists of practical scenarios and issues that are helpful to students and professionals
- Covers case studies using Verilog and use of Verilog to implement the ASIC and FPGA based designs
- Provides over 200 practical examples
- Request lecturer material: sn.pub/lecturer-material
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Table of contents (25 chapters)
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Front Matter
Keywords
About this book
This second edition focuses on the thought process of digital design and implementation in the context of VLSI and system design. It covers the Verilog 2001 and Verilog 2005 RTL design styles, constructs and the optimization at the RTL and synthesis level. The book also covers the logic synthesis, low power, multiple clock domain design concepts and design performance improvement techniques. The book includes 250 design examples/illustrations and 100 exercise questions. This volume can be used as a core or supplementary text in undergraduate courses on logic design and as a text for professional and vocational coursework. In addition, it will be a hands-on professional reference and a self-study aid for hobbyists.
Authors and Affiliations
About the author
Vaibbhav Taraate is an entrepreneur and mentor at “1 Rupee S T”. He holds B.E. (Electronics) degree from Shivaji University, Kolhapur (1995) and received a Gold Medal for standing first in all engineering branches. He completed his M.Tech. (Aerospace Control and Guidance) at the Indian Institute of Technology (IIT) Bombay, India, in 1999. He has over 18 years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog, VHDL and SystemVerilog. He has worked with multinational corporations as a consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis and optimization, static timing analysis, system design using microprocessors, high-speed VLSI designs, and architecture design of complex SOCs.
Bibliographic Information
Book Title: Digital Logic Design Using Verilog
Book Subtitle: Coding and RTL Synthesis
Authors: Vaibbhav Taraate
DOI: https://doi.org/10.1007/978-981-16-3199-3
Publisher: Springer Singapore
eBook Packages: Engineering, Engineering (R0)
Copyright Information: The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2022
Hardcover ISBN: 978-981-16-3198-6Published: 01 November 2021
Softcover ISBN: 978-981-16-3201-3Published: 02 November 2022
eBook ISBN: 978-981-16-3199-3Published: 31 October 2021
Edition Number: 2
Number of Pages: XXV, 604
Number of Illustrations: 123 b/w illustrations, 529 illustrations in colour
Topics: Circuits and Systems, Electronics and Microelectronics, Instrumentation, Logic Design