Abstract
During the ASIC synthesis, the objective is to get the gate-level netlist. The synthesis tool uses the optimization constraints, and these constraints are specified by using the SDC commands. The chapter discusses the ASIC synthesis and important SDC commands used during synthesis.
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© 2022 The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.
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Taraate, V. (2022). ASIC Synthesis and SDC Commands. In: Digital Logic Design Using Verilog. Springer, Singapore. https://doi.org/10.1007/978-981-16-3199-3_19
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DOI: https://doi.org/10.1007/978-981-16-3199-3_19
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Publisher Name: Springer, Singapore
Print ISBN: 978-981-16-3198-6
Online ISBN: 978-981-16-3199-3
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