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A Statistical Sampler for a New On-Line Analog Test Method

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Abstract

This work shows a new strategy to the on-line test of analog circuits. The technique presents a very low analog overhead and it is completely digital. In the System-on-Chip (SoC) environment the on-line test can be developed by using processing power already available in the system. As all the signal processing is done in the digital domain, it allows use of a purely digital tester or a digital BIST technique. The main principle of operation is based on the observation of statistical properties of the circuit under test. Since it has low analog power and performance overhead, the proposed technique can be used to analyze the output of several stages of complex analog systems without the use of switches or analog multiplexors for reconfiguration, and no additional AD converter is needed. This paper presents the fundamentals of the proposed test method and some experimental results illustrating the operation of the Statistical Sampler concerning linear analog systems.

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Authors and Affiliations

  1. Instituto de Informática-PPGC, Universidade Federal do Rio Grande do Sul, Porto Alegre, RS, Brasil

    Marcelo Negreiros, Luigi Carro & Altamiro A. Susin

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  1. Marcelo Negreiros
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  2. Luigi Carro
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  3. Altamiro A. Susin
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Negreiros, M., Carro, L. & Susin, A.A. A Statistical Sampler for a New On-Line Analog Test Method. Journal of Electronic Testing 19, 585–595 (2003). https://doi.org/10.1023/A:1025182115706

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  • DOI: https://doi.org/10.1023/A:1025182115706

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