Abstract
This paper presents an improved approach for testing and measuring the different parameters of an Analog to Digital Converter (ADC). The proposed methodology Pseudo-BIST is a combination of ATE (Automatic Test Equipment) and BIST (Built-In Self-Test). Pseudo-BIST provides a novel multi-processing technique where data conversion and calculation of static parameters takes place at the same instant. The proposed method has been applied to a SAR-ADC with test time reduction of more than 76% for a single site SAR-ADC and 93% reduction in time for 8 site ADCs. Pseudo-BIST also achieves a 50–70% reduction in area overhead as compared to BIST consisting of a high precision DAC.
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Acknowledgements
The authors would like to thank the DFT Team in Automotive and Discrete Group at ST Microelectronics, India for providing tools, technologies and for providing technical support throughout the work.
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Gupta, Y., Deb, S., Singh, V., Srinivasan, V.N., Sharma, M., Das, S. (2017). Pseudo-BIST: A Novel Technique for SAR-ADC Testing. In: Kaushik, B., Dasgupta, S., Singh, V. (eds) VLSI Design and Test. VDAT 2017. Communications in Computer and Information Science, vol 711. Springer, Singapore. https://doi.org/10.1007/978-981-10-7470-7_18
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DOI: https://doi.org/10.1007/978-981-10-7470-7_18
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