Abstract
This paper describes a novel method that can be used to reduce test cycle count in a parallel access scan based Built-In-Self-Test (BIST) environment. An algorithm that allows the efficient application of deterministically generated patterns is proposed. This approach allows BIST fault coverage to be increased using deterministic vectors, while minimizing the cost, in terms of test cycles, of applying the vectors.
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Ayari, B., Varma, P. Test Cycle Count Reduction in a Parallel Scan BIST Environment. Journal of Electronic Testing 16, 409–418 (2000). https://doi.org/10.1023/A:1008304329142
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DOI: https://doi.org/10.1023/A:1008304329142