Abstract
A new built-in self test BIST method is proposed for digital data processing circuits. The advantage of the proposed method is lower area overhead than for conventional BIST. On-line and off-line testing capabilities are used simultaneously to ensure more reliable testing. Some existing circuit blocks are reconfigured for test pattern generation and test response compaction. The circuit after the partitioning is tested mutually by its subparts. The results show significant area reduction and negligible fault coverage loss in comparison with conventional BIST.
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Acknowledgment
The work has been supported by Slovak national project VEGA 2/0135/08.
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Dobai, R., Baláž, M., Trebatický, P., Malik, P., Gramatová, E. (2013). A Low-Overhead BIST Architecture for Digital Data Processing Circuits. In: Sobh, T., Elleithy, K. (eds) Emerging Trends in Computing, Informatics, Systems Sciences, and Engineering. Lecture Notes in Electrical Engineering, vol 151. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-3558-7_56
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DOI: https://doi.org/10.1007/978-1-4614-3558-7_56
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