Insight into Threshold Voltage and Drain Induced Barrier Lowering in Negative Capacitance Field Effect Transistor

Abstract

In this paper, we have discussed threshold voltage and drain induced barrier lowering in NCFET. Threshold voltage in NCFET is lower as compared to MOSFET which is mainly because of negative equivalent oxide capacitance in NCFET. Further, we have discussed drain induced barrier lowering in NCFET and MOSFET. An increase in drain bias in MOSFET leads to decrease in threshold voltage and an increase in leakage current whereas in NCFET increase in drain bias leads to increase in threshold voltage and decrease in leakage current. We have obtained a positive value of DIBL factor for MOSFET and negative value for NCFET.

Appendix

To understand the effect of gate $(V_{G} )$ and drain $\left( {V_{D} } \right)$ bias on internal node voltage $(V_{MOS} )$, we need to study the equivalent capacitor model for NCFET shown in Fig. 5.

Fig. 5

a Equivalent capacitor model for NCFET at $V_{D} = 0$. b Equivalent capacitor model for NCFET at $V_{G} = 0$

Considering $V_{D} = 0$ and applying KCL at node $V_{MOS}^{a}$ leads to following equation:

$$VC_{D} + VC_{S} + VC_{dep} + \left( {V - V_{MOS}^{a} } \right)C_{ox} = 0$$

(16)

$$(V_{MOS}^{a} - V)C_{ox} + (V_{MOS}^{a} - V_{G} )C_{F} = 0$$

(17)

Solving the Eqs. (16) and (17)

$$V_{MOS}^{a} = \frac{{C_{F} V_{G} }}{{C_{F} + C_{MOS} }}$$

(18)

Considering the negative nature of the ferroelectric capacitor $V_{MOS}$ can be represented as:

$$V_{MOS}^{a} = \frac{{V_{G} }}{{1 - \frac{{C_{MOS} }}{{\left| {C_{F} } \right|}}}}$$

(19)

$$\frac{1}{{C_{MOS} }} = \frac{1}{{C_{ox} }} + \frac{1}{{C_{S} + C_{D} + C_{dep} }}$$

(20)

Considering $V_{G} = 0$ and applying KCL at node $V_{MOS}^{b}$ leads to the following equation:

$$\left( {V - V_{D} } \right)C_{D} + VC_{S} + VC_{dep} + \left( {V - V_{MOS}^{b} } \right)C_{ox} = 0$$

(21)

$$(V_{MOS}^{b} - V)C_{ox} + V_{MOS}^{b} C_{F} = 0$$

(22)

$$V_{MOS}^{b} = \frac{{C_{D} C_{MOS} V_{D} }}{{\left( {C_{S} + C_{D} + C_{dep} } \right)\left( {C_{F} + C_{MOS} } \right)}}$$

(23)

Since the condition for no hysteresis in NCFET is $C_{MOS} < \left| {C_{F} } \right|$ and to achieve sub-60 mV/decade subthreshold swing condition is $C_{ox} > \left| {C_{F} } \right|$. Now to achieve both the advantages the conditions become $C_{MOS} < \left| {C_{F} } \right| < C_{ox}$. Since $C_{ox}$ is greater than $C_{MOS}$. Equation (20) can be approximated as $C_{MOS} = C_{S} + C_{D} + C_{dep}$. Hence Eq. (23) can be written as:

$$V_{MOS}^{b} = \frac{{C_{D} V_{D} }}{{(C_{F} + C_{MOS} )}}$$

(24)

Considering the negative nature of the ferroelectric capacitor $V_{MOS}$ can be represented as:

$$V_{MOS}^{b} = \frac{{V_{D} }}{{\frac{{\left| {C_{F} } \right| - C_{MOS} }}{{ - C_{D} }}}}$$

(25)

$V_{MOS}$ can be expressed as follows:

$$V_{MOS} = V_{MOS}^{a} + V_{MOS}^{b}$$

(26)

$$V_{MOS} = \frac{{\left| {C_{F} } \right|V_{G} }}{{\left| {C_{F} } \right| - C_{MOS} }} + \frac{{ - C_{D} V_{D} }}{{\left| {C_{F} } \right| - C_{MOS} }}$$

(27)