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Understanding negative differential resistance and region of operation in undoped HfO2-based negative capacitance field effect transistor

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Abstract

In this paper, we have discussed, negative differential resistance and region of operation in Negative Capacitance Field Effect Transistor. NDR occurs in drain characteristics because of coupling between drain voltage and internal gate voltage via gate to drain capacitance. NDR is more pronounced in NCFET at low gate bias and higher ferroelectric thickness. At these conditions internal voltage starts decreasing with increase in drain bias which is responsible for non-saturation or decrease in drain current with positive incremental change in drain bias which is termed as NDR. NDR in drain characteristics also leads to negative output conductance in NCFET. Negative value of output conductance occurs because of negative drain coupling factor in NCFET. Negative value of drain coupling factor is a necessary condition for hysteresis free operation. Also Gummel Symmetry Test has been done to validate the model. Further we have discussed about region of operation in NCFET and resistive load inverter based on NCFET.

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References

  1. A. Rusu, G.A. Salvatore, D. Jimenez, A.M. Ionescu, Metal-ferroelectric-meta-oxide-semiconductor field effect transistor with sub-60 mV/decade subthreshold swing and internal voltage amplification. 2010 Int. Electron Dev. Meet. (2010). https://doi.org/10.1109/iedm.2010.5703374

    Article  Google Scholar 

  2. G.A. Salvatore, D. Bouvet, A.M. Ionescu, Demonstration of subthrehold swing smaller than 60 mV/decade in Fe-FET with P(VDF-TrFE)/SiO2 gate stack. IEEE Int. Electron Dev. Meet. 2008, 1–4 (2008). https://doi.org/10.1109/iedm.2008.4796642

    Article  Google Scholar 

  3. S. Salahuddin, S. Datta, Use of negative capacitance to provide voltage amplification for low power nanoscale devices. Nano Lett. 8(2), 405–410 (2008). https://doi.org/10.1021/nl071804g

    Article  ADS  Google Scholar 

  4. G. Catalan, D. Jiménez, A. Gruverman, Ferroelectrics: negative capacitance detected. Nat. Mater. 14(2), 137–139 (2015). https://doi.org/10.1038/nmat4195

    Article  ADS  Google Scholar 

  5. D.J.R. Appleby, N.K. Ponon, S.K.K. Kwa, B. Zou, P.K. Petrov, T. Wang, N.M. Alford, A. O’Neill, Experimental observation of negative capacitance in ferroelectrics at room temperature. Nano Lett. 14(7), 3864–3868 (2014). https://doi.org/10.1021/nl5017255

    Article  ADS  Google Scholar 

  6. A. Saeidi, F. Jazaeri, I. Stolichnov, A.M. Ionescu, Double-gate negative-capacitance MOSFET with PZT gate-stack on ultra thin body SOI: an experimentally calibrated simulation study of device performance. IEEE Trans. Electron Devices 63(12), 4678–4684 (2016). https://doi.org/10.1109/ted.2016.2616035

    Article  ADS  Google Scholar 

  7. V.V. Zhirnov, R.K. Cavin, Nanoelectronics: negative capacitance to the rescue? Nat. Nanotechnol. 3(2), 77–78 (2008). https://doi.org/10.1038/nnano.2008.18

    Article  ADS  Google Scholar 

  8. C.W. Yeung, A.I. Khan, A. Sarker, S. Salahuddin, C. Hu, Low power negative capacitance FETs for future quantum-well body technology. In 2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), Hsinchu, pp 1–2 (2013). https://doi.org/10.1109/vlsi-tsa.2013.6545648

  9. A. Jain, M.A. Alam, Stability constraints define the minimum subthreshold swing of a negative capacitance field-effect transistor. IEEE Trans. Electron Devices 61(7), 2235–2242 (2014). https://doi.org/10.1109/ted.2014.2316167

    Article  Google Scholar 

  10. G. Pahwa, T. Dutta, A. Agarwal, S. Khandelwal, S. Salahuddin, C. Hu, Y.S. Chauhan, Analysis and compact modeling of negative capacitance transistor with high ON-current and negative output differential resistance—part II: model validation. IEEE Trans. Electron Devices 63(12), 4986–4992 (2016). https://doi.org/10.1109/ted.2016.2614436

    Article  ADS  Google Scholar 

  11. H.-P. Chen, V.C. Lee, A. Ohoka, J. Xiang, Y. Taur, Modeling and design of ferroelectric MOSFETs. IEEE Trans. Electron Devices 58(8), 2401–2405 (2011). https://doi.org/10.1109/ted.2011.2155067

    Article  ADS  Google Scholar 

  12. D. Jiménez, E. Miranda, A. Godoy, Analytic model for the surface potential and drain current in negative capacitance field-effect transistors. IEEE Trans. Electron Devices 57(10), 2405–2409 (2010). https://doi.org/10.1109/ted.2011.2149532

    Article  ADS  Google Scholar 

  13. C.-I. Lin, A.I. Khan, S. Salahuddin, C. Hu, Effects of the variation of ferroelectric properties on negative capacitance FET characteristics. IEEE Trans. Electron Devices 63(5), 2197–2199 (2016). https://doi.org/10.1109/ted.2016.2514783

    Article  ADS  Google Scholar 

  14. B. Awadhiya, P.N. Kondekar, A.D. Meshram, Passive voltage amplification in non-leaky ferroelectric–dielectric heterostructure. Micro Nano Lett. 13(10), 1399–1403 (2018). https://doi.org/10.1049/mnl.2018.5172

    Article  Google Scholar 

  15. Y. Li, K. Yao, G.S. Samudra, Delay and power evaluation of negative capacitance ferroelectric MOSFET BASED on SPICE model. IEEE Trans. Electron Devices 64(5), 2403–2408 (2017)

    Article  ADS  Google Scholar 

  16. J. Zhou, G. Han, J. Li, Y. Liu, Y. Peng, J. Zhang, Q.Q. Sun, D.W. Zhang, Y. Hao, Negative differential resistance in negative capacitance FETs. IEEE Electron Device Lett. 39(4), 622–625 (2018). https://doi.org/10.1109/led.2018.2810071

    Article  ADS  Google Scholar 

  17. K. Hess, H. Morkoç, H. Shichijo, B.G. Streetman, Negative differential resistance through real-space electron transfer. Appl. Phys. Lett. 35(6), 469–471 (1979). https://doi.org/10.1063/1.91172

    Article  ADS  Google Scholar 

  18. J.C. Scott, L.D. Bozano, Nonvolatile memory elements based on organic materials. Adv. Mater. 19(11), 1452–1463 (2007)

    Article  Google Scholar 

  19. M. Prezioso, A. Riminucci, I. Bergenti, P. Graziosi, D. Brunel, V.A. Dediu, Electrically programmable magnetoresistance in multifunctional organic-based spin valve devices. Adv. Mater. 23(11), 1371–1375 (2011)

    Article  Google Scholar 

  20. J. Seo, J. Lee, M. Shin, Analysis of drain-induced barrier rising in short-channel negative-capacitance FETs and its applications. IEEE Trans. Electron Devices 64(4), 1793–1798 (2017). https://doi.org/10.1109/ted.2017.2658673

    Article  ADS  Google Scholar 

  21. H. Agarwal, P. Kushwaha, J.P. Duarte, Y.K. Lin, A.B. Sachid, H.L. Chang, S. Salahuddin, C. Hu, Designing 0.5 V 5-nm HP and 0.23 V 5-nm LP NC-FinFETs with improved IOFF sensitivity in presence of parasitic capacitance. IEEE Trans. Electron Devices 65(3), 1211–1216 (2018). https://doi.org/10.1109/ted.2018.2790349

    Article  ADS  Google Scholar 

  22. H. Agarwal, P. Kushwaha, J.P. Duarte, Y.K. Lin, A.B. Sachid, M.Y. Kao, H.L. Chang, S. Salahuddin, C. Hu, Engineering negative differential resistance in NCFETs for analog applications. IEEE Trans. Electron Devices 65(5), 2033–2039 (2018). https://doi.org/10.1109/ted.2018.2817238

    Article  ADS  Google Scholar 

  23. J. Zhou, G. Han, Q. Li, Y. Peng, X. Lu, C. Zhang, J. Zhang, Q.Q. Sun, D.W. Zhang, Y. Hao, Ferroelectric HfZrOx Ge and GeSn PMOSFETs with sub-60 mV/decade subthreshold swing, negligible hysteresis, and improved IDS. IEDM Tech. Dig. (2016). https://doi.org/10.1109/iedm.2016.7838401

    Article  Google Scholar 

  24. Muhammad AW, Muhammad AA, A Verilog-A compact model for negative capacitance FET. (Version 1.1.3). nanoHUB (2017). https://doi.org/10.4231/d3qz22k3z

  25. P. Polakowski, J. Muller, Ferroelectricity in undoped hafnium oxide. Appl. Phys. Lett. 106(23), 232905 (2015). https://doi.org/10.1063/1.4922272

    Article  ADS  Google Scholar 

  26. K.D. Kim, M.H. Park, H.J. Kim, Y.J. Kim, T. Moon, Y.H. Lee, S.D. Hyun, T. Gwon, C.S. Hwang, Ferroelectricity in undoped-HfO2 thin films induced by deposition temperature control during atomic layer deposition. J. Mater. Chem. C 4(28), 6864–6872 (2016). https://doi.org/10.1039/c6tc02003h

    Article  Google Scholar 

  27. Synopsys HSPICE Version L-2016.03-1 https://www.synopsys.com//verification/ams-verification/hspice.html

  28. L. D. Landau, I. M. Khalatnikov, On the anomalous absorption of sound near a second order phase transition point, in Collected Papers of L.D. Landau (Elsevier, pp. 626–629, 1965) . https://doi.org/10.1016/b978-0-08-010586-4.50087-0

  29. T.K. Song, Landau-Khalatnikov simulations for ferroelectric switching in ferroelectric random access memory application. J. Korean Phys. Soc. 46(1), 5–9 (2005)

    Google Scholar 

  30. A.I. Khan, K. Chatterjee, B. Wang, S. Drapcho, L. You, C. Serrao, S.R. Bakaul, R. Ramesh, S. Salahuddin, Negative capacitance in a ferroelectric capacitor. Nat. Mater. 14(2), 182–186 (2015). https://doi.org/10.1038/nmat4148

    Article  ADS  Google Scholar 

  31. A.I. Khan, U. Radhakrishna, K. Chatterjee, S. Salahuddin, D.A. Antoniadis, Negative capacitance behavior in a leaky ferroelectric. IEEE Trans. Electron Devices 63(11), 4416–4422 (2016). https://doi.org/10.1109/ted.2016.2612656

    Article  ADS  Google Scholar 

  32. S. George, A. Aziz, X. Li, M. S. Kim, S. Datta, J. Sampson, S. Gupta and V. Narayanan., “Device Circuit Co Design of FEFET Based Logic for Low Voltage Processors,” in 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016, pp. 649–654. https://doi.org/10.1109/isvlsi.2016.116

  33. S. George, A. Aziz, X. Li, J. Sampson, S. Datta, S. Gupta, and V. Narayanan, “NCFET based logic for energy harvesting systems,” SRC TECHCON, 2015, pp. 1–4

  34. S. Gupta, M. Steiner, A. Aziz, V. Narayanan, S. Datta, S.K. Dupta, Device-circuit analysis of ferroelectric FETs for low-power logic. IEEE Trans. Electron Devices 64(8), 3092–3100 (2017). https://doi.org/10.1109/ted.2017.2717929

    Article  ADS  Google Scholar 

  35. G.H. See, X. Zhou, K. Chandrasekaran, B.S. Chiah, Z. Zhu, C. Wei, S. Lin, G. Zhu, G.H. Lim, A compact model satisfying gummel symmetry in higher order derivatives and applicable to asymmetric MOSFETs. IEEE Trans. Electron Devices 55(2), 624–631 (2008). https://doi.org/10.1109/ted.2007.912951

    Article  ADS  Google Scholar 

  36. C.C. Mcandrew, Validation of MOSFET model source-drain symmetry. IEEE Trans. Electron Devices 53(9), 2202–2206 (2006). https://doi.org/10.1109/ted.2006.881005

    Article  ADS  Google Scholar 

  37. K. Singh, A.B. Bhattacharyya, Gummel symmetry test on charge based drain current expression using modified first-order hyperbolic velocity-field expression. Solid State Electron. 129, 188–195 (2017). https://doi.org/10.1016/j.sse.2016.11.006

    Article  ADS  Google Scholar 

  38. D. Neamen, Semiconductor physics and devices (McGraw-Hill Inc, New York, 2003)

    Google Scholar 

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Acknowledgements

The authors would like to thank Dr. Muhammad Abdul Wahab (Intel Corporation) and Prof. Muhammad Ashraful Alam (Purdue University) for providing the NCFET model available at NANO HUB.

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  1. PDPM-Indian Institute of Information Technology, Design and Manufacturing Jabalpur, Jabalpur, MP, 482005, India

    Bhaskar Awadhiya, Pravin N. Kondekar & Ashvinee Deo Meshram

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Awadhiya, B., Kondekar, P.N. & Meshram, A.D. Understanding negative differential resistance and region of operation in undoped HfO2-based negative capacitance field effect transistor. Appl. Phys. A 125, 427 (2019). https://doi.org/10.1007/s00339-019-2718-2

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