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Ultra Steep Ge-Source Dopingless Tunnelling Field Effect Transistor with Enhanced Drive Current: DC to Linearity Characteristics Analysis

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Abstract

Ge-source dopingless tunnelling field effect transistor (Ge-source DLTFET) with the optimization of dielectric oxide thickness under the source and the gate contacts is proposed and investigated by calibrated 2D TCAD device simulation. As the structure is realized using dopingless technique, this enables lower thermal budget, higher immunity towards the random dopant fluctuations (RDFs) effects and velocity degradation effects. The optimization of dielectric thickness has been done to tune the carrier concentrations induced in source and channel regions in order to improve the device performance. The drive current is magnificently enhanced along with ION/IOFF ratio, peak transconductance and ultra-steep subthreshold slope (SS) is reported for the optimized Si-DLTFET. In addition to this by deploying Ge-source instead of Si source in optimized Si-DLTFET increases ON current slightly and OFF current gets reduced by the order of two as compared to the optimized Si-DLTFET. This improves the ION/IOFF ratio, the reported drive current for Ge-source DLTFET is 5.1 × 10−4 A/μm, along with ION/IOFF ratio as 1.54 × 1013, peak transconductance as 1.26 mS/μm and ultra-steep SS as 1.69 mV/decade. Further, the analog, RF and linearity performance parameters have also been investigated for both the structures and demonstrated notable improvement. The energy efficiency investigation reveals a significant reduction in energy-delay product. Further the linearity analysis is also presented for the reported device structure. This paper indicates the potentials of optimized Si-DLTFET and Ge-source DLTFET as promising candidates for low power analog and RF applications and Ge-source DLTFET has better device dc performance.

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Acknowledgements

The authors are grateful to the National Institute of Technology, Jamshedpur, India for providing the computational resources.

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Authors and Affiliations

  1. Microelectronics & VLSI Design Lab, National Institute of Technology Patna, Patna, India

    Kumari Nibha Priyadarshani & Sangeeta Singh

  2. National Institute of Technology Jamshedpur, Jamshedpur, India

    Kunal Singh

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  1. Kumari Nibha Priyadarshani
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  2. Sangeeta Singh
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  3. Kunal Singh
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Sangeeta Singh.

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National Institute of Technology Patna, India.

National Institute of Technology Patna, India.

National Institute of Technology Jamshedpur, India.

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Priyadarshani, K.N., Singh, S. & Singh, K. Ultra Steep Ge-Source Dopingless Tunnelling Field Effect Transistor with Enhanced Drive Current: DC to Linearity Characteristics Analysis. Silicon 14, 5863–5876 (2022). https://doi.org/10.1007/s12633-021-01339-2

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