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A novel electrostatically doped ferroelectric Schottky barrier tunnel FET: process resilient design

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Abstract

This work investigates a process-variation resilient electrostatically-doped ferroelectric Schottky-barrier tunnel FET (ED-FE-SB-TFET) based on negative capacitance (NC). The key attributes of ED-FE-SB-TFET are perovskite ferroelectric (FE) gate stack-induced NC behavior and electrostatic doping to induce pockets at both source/drain and channel interfaces. The positive feedback among the electric dipoles in FE material leads to intrinsic voltage amplification and enhanced gate controllability, thus it facilitates faster switching transitions. The proposed ED-FE-SB-TFET endeavors to create a substantial reduction in the ambipolar current (\(I_\mathrm{Amb}\)), steep sub-threshold slope, paramount boost in drive current, lower drain-induced barrier-lowering, and enhanced scalability. It also obviates the need for metallurgical doping, hence ion-implantation or dopant segregation techniques employed for planar SB-TFETs pocket-doping are no longer required, and it also modifies effective Schottky barrier height and Schottky tunneling barrier width significantly to enhance the device behavior. It offers a simplified fabrication process, and it is highly resilient towards process variations, doping control issues, and random dopant fluctuations. Moreover, there is a reduced thermal budget that facilitates its fabrication on single crystal silicon-on-glass substrate realized by wafer scale epitaxial transfer. Results reveal its potential as strong candidate for next generation, scaled and low power applications.

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Acknowledgements

Authors are thankful to Dr. Neeraj K. Jaiswal, faculty of Physics at PDPM-Indian Institute of Information Technology, Design and Manufacturing, Jabalpur, India, for his guidance in device physics. We also thank PDPM Indian Institute of Information Technology, Design and Manufacturing, Jabalpur for providing infrastructure facilities.

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Authors and Affiliations

  1. Department of Electronics and Communication, Indian Institute of Information Technology, Kota, India

    Sangeeta Singh

  2. Nanoelectronics and VLSI Laboratory, Indian Institute of Information Technology, Design and Manufacturing, Jabalpur, India

    P. N. Kondekar

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  1. Sangeeta Singh
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  2. P. N. Kondekar
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Correspondence to Sangeeta Singh.

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Singh, S., Kondekar, P.N. A novel electrostatically doped ferroelectric Schottky barrier tunnel FET: process resilient design. J Comput Electron 16, 685–695 (2017). https://doi.org/10.1007/s10825-017-0987-6

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  • DOI: https://doi.org/10.1007/s10825-017-0987-6

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