Skip to main content

Advertisement

SpringerLink
Log in

Reconfigurable Rounding Based Approximate Multiplier for Energy Efficient Multimedia Applications

  • Published:
Wireless Personal Communications Aims and scope Submit manuscript

Abstract

The approximate design has emerged as a revolutionary design paradigm to obtain energy efficient digital signal processing cores while exhibiting acceptable accuracy. In different signal processing architectures, multiplier is the prime arithmetic unit and significantly influences the performance of these cores. Therefore, four novel energy efficient rounding based approximate (RBA) multiplier architectures are proposed in this paper. These multipliers first approximate input operands to the nearest power of two values and then achieve multiplication using few adders and shifters. The proposed RBA multipliers significantly reduce implementation complexity and provide higher energy efficiency. Further, a novel reconfigurable rounding based approximate (RRBA) multiplier is proposed to achieve desired performance-quality tradeoff. Further, the performance of proposed RBA and RRBA multipliers is evaluated and analysed over the existing approximate multiplier architectures. The proposed 8-bit RBA0 requires 59.8% (54.7%) reduced area (delay) compared to the existing approximate multiplier. Finally, the efficacy of the proposed multipliers is demonstrated in the application by implementing Gaussian filters embedded with existing and proposed approximate multipliers. The Gaussian filter designed using RBA0 provides 32.5% reduced energy consumption over the filter with existing multiplier.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6

Similar content being viewed by others

References

  1. Mittal, S. (2016). A survey of techniques for approximate computing. ACM Computing Surveys (CSUR), 48(4), 62.

    Google Scholar 

  2. Narayanamoorthy, S., Moghaddam, H. A., Liu, Z., Park, T., & Kim, N. S. (2015). Energy-efficient approximate multiplication for digital signal processing and classification applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(6), 1180–1184.

    Article  Google Scholar 

  3. Hashemi, S., Bahar, R., & Reda, S. (2015). Drum: A dynamic range unbiased multiplier for approximate applications. In Proceedings of the IEEE/ACM international conference on computer-aided design (pp. 418–425). IEEE Press.

  4. Zendegani, R., Kamal, M., Bahadori, M., Afzali-Kusha, A., & Pedram, M. (2017). ROBA multiplier: A rounding-based approximate multiplier for high-speed yet energy-efficient digital signal processing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(2), 393–401.

    Article  Google Scholar 

  5. Leon, V., Zervakis, G., Soudris, D., & Pekmestzi, K. (2018). Approximate hybrid high radix encoding for energy-efficient inexact multipliers. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(3), 421–430.

    Article  Google Scholar 

  6. Akbari, O., Kamal, M., Afzali-Kusha, A., & Pedram, M. (2017). Dual-quality 4:2 compressors for utilizing in dynamic accuracy configurable multipliers. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(4), 1352–1361.

    Article  Google Scholar 

  7. Ha, M., & Lee, S. (2018). Multipliers with approximate 4–2 compressors and error recovery modules. IEEE Embedded Systems Letters, 10(1), 6–9.

    Article  Google Scholar 

  8. Marimuthu, R., Rezinold, Y. E., & Mallick, P. (2017). Design and analysis of multiplier using approximate 15–4 compressor. IEEE Access, 5, 1027–1036.

    Article  Google Scholar 

  9. Esposito, D., Strollo, A. G. M., Napoli, E., De Caro, D., & Petra, N. (2018). Approximate multipliers based on new approximate compressors. IEEE Transactions on Circuits and Systems I: Regular Papers, 99, 1–14.

    Google Scholar 

  10. Esposito, D., De Caro, D., Napoli, E., Petra, N., & Strollo, A. G. (2017). On the use of approximate adders in carry-save multiplier-accumulators. In 2017 IEEE international symposium on circuits and systems (ISCAS) (pp. 1–4). IEEE.

  11. Kyaw, K. Y., Goh, W.-L., & Yeo, K.-S. (2010). Low-power high-speed multiplier for error-tolerant application. In 2010 IEEE international conference of electron devices and solid-state circuits (EDSSC) (pp. 1–4).

  12. Garg, B., & Sharma, G. (2016). Low power signal processing via approximate multiplier for error-resilient applications. In 2016 11th international conference on industrial and information systems (ICIIS) (pp. 546–551). IEEE.

  13. Kulkarni, P., Gupta, P., & Ercegovac, M. (2011). Trading accuracy for power with an underdesigned multiplier architecture. In 24th international conference on VLSI design (VLSI design), 2011 (pp. 346–351).

  14. Garg, B., & Sharma, G. (2017). ACM: An energy-efficient accuracy configurable multiplier for error-resilient applications. Journal of Electronic Testing, 33(4), 479–489.

    Article  Google Scholar 

  15. Garg, B., Patel, S. K., & Dutt, S. (2020). Loba: A leading one bit based imprecise multiplier for efficient image processing. Journal of Electronic Testing-Theory and Applications, 36, 429–437.

    Article  Google Scholar 

  16. Van Toan, N., & Lee, J.-G. (2020). FPGA-based multi-level approximate multipliers for high-performance error-resilient applications. IEEE Access, 8, 25 481–25 497.

    Article  Google Scholar 

  17. Goswami, S. S. P., Paul, B., Dutt, S., & Trivedi, G. (2020). Comparative review of approximate multipliers. In 2020 30th international conference radioelektronika (radioelektronika) (pp. 1–6). IEEE.

  18. Vahdat, S., Kamal, M., Afzali-Kusha, A., & Pedram, M. (2019). TOSAM: An energy-efficient truncation-and rounding-based scalable approximate multiplier. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(5), 1161–1173.

    Article  Google Scholar 

  19. Alouani, I., Ahangari, H., Ozturk, O., & Niar, S. (2017). A novel heterogeneous approximate multiplier for low power and high performance. IEEE Embedded Systems Letters, 10(2), 45–48.

    Article  Google Scholar 

  20. Wang, J.-P., Kuang, S.-R., & Liang, S.-C. (2011). High-accuracy fixed-width modified booth multipliers for lossy applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19(1), 52–60.

    Article  Google Scholar 

  21. Farshchi, F., Abrishami, M., & Fakhraie, S. (2013). New approximate multiplier for low power digital signal processing. In 2013 17th CSI international symposium on computer architecture and digital systems (CADS) (pp. 25–30).

  22. Liu, W., Qian, L., Wang, C., Jiang, H., Han, J., & Lombardi, F. (2017). Design of approximate radix-4 booth multipliers for error-tolerant computing. IEEE Transactions on Computers, 66(8), 1435–1441.

    Article  MathSciNet  Google Scholar 

  23. Venkatachalam, S., Lee, H. J., & Ko, S.-B. (2018). Power efficient approximate booth multiplier. In 2018 IEEE international symposium on circuits and systems (ISCAS) (pp. 1–4). IEEE.

  24. Leon, V., Zervakis, G., Soudris, D., & Pekmestzi, K. (2017). Approximate hybrid high radix encoding for energy-efficient inexact multipliers. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(3), 421–430.

    Article  Google Scholar 

  25. Garg, B., & Sharma, G. (2016). A quality-aware energy-scalable Gaussian smoothing filter for image processing applications. Microprocessors and Microsystems, 45, 1–9.

    Article  Google Scholar 

  26. Liang, J., Han, J., & Lombardi, F. (2011). New metrics for the reliability of approximate and probabilistic adders. IEEE Transactions on Computers, 99, 1.

    MATH  Google Scholar 

  27. Wang, Z., Bovik, A., Sheikh, H., & Simoncelli, E. (2004). Image quality assessment: From error visibility to structural similarity. IEEE Transactions on Image Processing, 13(4), 600–612.

    Article  Google Scholar 

  28. Jaiswal, A., Garg, B., Kaushal, V., & Sharma, G. (2015). SPAA-aware 2D Gaussian smoothing filter design using efficient approximation techniques. In 2015 28th international conference on VLSI design (VLSID) (pp. 333–338). IEEE.

Download references

Author information

Authors and Affiliations

  1. Thapar Institute of Engineering and Technology, Patiala, India

    Bharat Garg & Sujit Patel

Authors
  1. Bharat Garg
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Sujit Patel
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Bharat Garg.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Garg, B., Patel, S. Reconfigurable Rounding Based Approximate Multiplier for Energy Efficient Multimedia Applications. Wireless Pers Commun 118, 919–931 (2021). https://doi.org/10.1007/s11277-020-08051-1

Download citation

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11277-020-08051-1

Keywords

Search

Navigation