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Design and Performance Analysis of Rounding Approximate Multiplier for Signal Processing Applications

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Smart Intelligent Computing and Applications

Part of the book series: Smart Innovation, Systems and Technologies ((SIST,volume 160))

Abstract

In the present work, a high speed and energy saving approximate multiplier is proposed. It reduces the computational complexity by rounding off the operands to the nearest exponent equivalent values of two. As a result, the processing time is reduced with high energy efficiency at the cost of introducing roundoff error. The performance of the proposed multiplier is evaluated and compared with the existing ones. The proposed approximate multiplier is also applied to filters.

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Authors and Affiliations

  1. Department of Electronics and Communications, Shri Vishnu Engineering College for Women, (Autonomous), Bhimavaram, India

    V. Naga Sravanthi & Sudheer Kumar Terlapu

Authors
  1. V. Naga Sravanthi
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  2. Sudheer Kumar Terlapu
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Corresponding author

Correspondence to Sudheer Kumar Terlapu .

Editor information

Editors and Affiliations

  1. School of Computer Engineering, KIIT Deemed to be University, Bhubaneswar, Odisha, India

    Suresh Chandra Satapathy

  2. Department of Electronics and Communication Engineering, Shri Ramswaroop Memorial Group of Professional Colleges, Lucknow, Uttar Pradesh, India

    Vikrant Bhateja

  3. School of Computer Applications, KIIT Deemed to be University, Bhubaneswar, Odisha, India

    J. R. Mohanty

  4. School of Computer and Information Science, University of Hyderabad, Hyderabad, Telangana, India

    Siba K. Udgata

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Naga Sravanthi, V., Terlapu, S.K. (2020). Design and Performance Analysis of Rounding Approximate Multiplier for Signal Processing Applications. In: Satapathy, S., Bhateja, V., Mohanty, J., Udgata, S. (eds) Smart Intelligent Computing and Applications . Smart Innovation, Systems and Technologies, vol 160. Springer, Singapore. https://doi.org/10.1007/978-981-32-9690-9_41

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