Skip to main content
Log in

Tolerating Soft Errors with Horizontal-Vertical-Diagonal-N-Queen (HVDNQ) Parity

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

A new error detection and correction methodology, defined as Horizontal-Vertical-Diagonal-N-Queen-Parity (HVDNQ), is proposed in this paper. This approach relies on five different types of parities: horizontal parity, vertical parity, forward diagonal parity, backward diagonal parity, and queen parity. This method works on an N X N cell area and can correct multi-bit upsets. The experimental analysis validates the effectiveness of the proposed methodology by comparing its efficiency with existing methodologies. In different varieties of error patterns such as equilateral triangle, pentagon, hexagon etc., the capability of error detection and correction of HVDNQ is much better than existing methods.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11

Similar content being viewed by others

References

  1. Siddiqui MSM, Ruchi S, Van Le L, Yoo T, Chang IJ, Kim TTH (2020) SRAM Radiation Hardening through Self-Refresh Operation and Error Correction. IEEE Trans Device Mater Reliab. https://doi.org/10.1109/TDMR.2020.2994769

    Article  Google Scholar 

  2. Junlong Z, Jin S, Xiumin Z, Tongquan W, Mingsong C, Shiyan H, Xiaobo, Sharon H (2018) Resource management for improving soft-error and lifetime reliability of real-time MPSoCs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 38(12):2215–2228. https://doi.org/10.1109/TCAD.2018.2883993

  3. Sadi et al. (2018) A New Approach to Tolerate Soft Errors by Using Triple Modular Redundancy. J Inf Technol 7(1):1–7

    Google Scholar 

  4. Wu J (2016) Energy efficient dual execution mode scheduling for real-time tasks with shared resources. Comput Syst Sci Eng 31(3):239–253. https://doi.org/10.1016/j.future.2015.05.012

    Article  Google Scholar 

  5. Nan H, Choi K (2012) High performance, low cost, and robust soft error tolerant latch designs for nanoscale CMOS technology. IEEE Trans Circuits Syst I Regul Pap 59(7):1445–1457. https://doi.org/10.1109/TCSI.2011.2177135

    Article  MathSciNet  Google Scholar 

  6. Wang F, Agrawal, VD (2008) Soft error rate determination for nanometer CMOS VLSI logic. In Proceedings 40th Southeastern Symposium on System Theory (SSST), pp. 324-328. https://doi.org/10.1109/SSST.2008.4480247

  7. Crouzet Y, Collet J, Arlat J (2005) Mitigating soft errors to prevent a hard threat to dependable computing. In Proceedings 11th IEEE International On-Line Testing Symposium. https://doi.org/10.1109/IOLTS.2005.42

  8. Muhammad SS, Palash KB, Palash G, Muhammed SR (2013) A new error correction coding approach. J Adv Inf Technol 4:142–147

  9. Hentschke R, Marques F, Lima F, Carro L, Susin A, Reis R (2002) Analyzing area and performance penalty of protecting different digital modules with Hamming code and triple modular redundancy. In Proceedings 15th Symposium on Integrated Circuits and Systems Design. https://doi.org/10.1109/SBCCI.2002.1137643

  10. Muhammad SS, Myers DG, Cesar OS (2010) Component Criticality Analysis to Minimizing Soft Errors Risk. In International Journal of Computer Systems Science and Engineering, CRL Publishing, 25:5

  11. Ferreyra PA, Marques CA, Ferreyra RT, Gaspar JP (2005) Failure map functions and accelerated mean time to failure tests: New approaches for improving the reliability estimation in systems exposed to single-event upsets. IEEE Trans Nucl Sci. 52(1):494–500. https://doi.org/10.1109/TNS.2005.845883

  12. Rubinoff M (1961) n-dimensional codes for detecting and correcting multiple errors0. Commun ACM 4(12):545–551. https://doi.org/10.1145/366853.366878

    Article  MathSciNet  MATH  Google Scholar 

  13. Imran M, Al-Ars Z, Gaydadjiev GN (2009) Improving soft error correction capability of 4-d parity codes. In Proceedings 14th IEEE European Test Symposium

  14. Dubney GO (2005) IS Reed Decoding the (23, 12, 7) Golay code using bit-error probability estimates. In Proceedings GLOBECOM. IEEE Global Telecommunications Conference. https://doi.org/10.1109/GLOCOM.2005.1577867

  15. Sakib A, Muhammad SS, Md. Shamimur R, Jan J (2017) Soft Error Tolerance using HVDQ (Horizontal-Vertical-Diagonal-Queen parity method). International Journal of Computer Systems Science and Engineering, CRL Publishing, 32(1):35–47

  16. Sumaiya M, Dewan, Sadi MS (2019) Soft Error Tolerance using Horizontal, Vertical, Diagonal and Seven Queen Parity. In Proceedings IEEE International Conference on Signal Processing, Information, Communication & Systems (SPICSCON), Dhaka, Bangladesh, pp. 114–117. https://doi.org/10.1109/SPICSCON48833.2019.9064971

  17. Pflanz M, Walther K, Galke C, Vierhaus HT (2003) On-line techniques for error detection and correction in processor registers with cross-parity check. J Electron Test 19(5):501–510. https://doi.org/10.1023/A:1025165712071

    Article  Google Scholar 

  18. Sharma S, Vijayakumar P (2012) An hvd based error detection and correction of soft errors in semiconductor memories used for space applications. In International Conference on Devices, Circuits and Systems (ICDCS). IEEE. https://doi.org/10.1109/ICDCSyst.2012.6188771

  19. Anne NB, Thirunavukkarasu U, Latifi S (2004) Three and four-dimensional parity-check codes for correction and detection of multiple errors. In Proceedings International Conference on Information Technology: Coding and Computing (ITCC). https://doi.org/10.1109/ITCC.2004.1286763

  20. Aflakian D, Siddiqui T, Khan NA, Aflakia D (2011) Error detection and correction over two-dimensional and two-diagonal model and five-dimensional model. Int J Adv Comput Sci Appl (IJACSA) 2(7)

  21. Kishani M, Zarandi HR, Pedram H, Tajary A (2011) HVD: horizontal-vertical-diagonal error detecting and correcting code to protect against with soft errors. Des Autom Embed Syst 15(3–4):289–310

    Article  Google Scholar 

  22. Argyrides C, Pradhan DK, Kocak T (2009) Matrix codes for reliable and cost efficient memory chips. IEEE Trans Very Large Scale Integr (VLSI) Syst 19(3)420–428. https://doi.org/10.1109/TVLSI.2009.2036362

  23. Silva F, Freitas W, Silveira J, Marcon C, Vargas F (2020) Extended Matrix Region Selection Code: An ECC for adjacent Multiple Cell Upset in Memory Arrays. Microelectron Reliab 106:113582. https://doi.org/10.1016/j.microrel.2020.113582

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Muhammad Sheikh Sadi.

Additional information

Responsible Editor: F. L. Vargas

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Sadi, M., Sumaiya, S., Dewan, M. et al. Tolerating Soft Errors with Horizontal-Vertical-Diagonal-N-Queen (HVDNQ) Parity. J Electron Test 37, 243–254 (2021). https://doi.org/10.1007/s10836-021-05942-4

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-021-05942-4

Keywords

Navigation