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Single and double-adjacent error correcting code (SDECC) with lower design overheads and mis-correction rate for SRAMs

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Abstract

Reliability of Static Random Access Memories (SRAMs) is immensely affected by radiation induced soft errors. Multiple Cell Upsets (MCUs) are caused by these soft errors and this lead to data corruption in several SRAM cells. Error Correcting Codes are normally exploited to alleviate the effect of MCUs. Single Error Correction–Double Error Detection (SEC–DED) codes are not the appropriate preference against MCUs rather these codes are suitable for protecting SRAM cells against Single Cell Upset. Single Error Correction–Double Error Detection–Double Adjacent Error Correction (SEC–DED–DAEC) codes are more suitable due to increasing trends of single and double-adjacent errors in SRAM cells. In this paper, a new SEC–DED–DAEC code has been proposed which is proficient of correcting single and double-adjacent errors in SRAMs. Our newly proposed code has been termed as Single and Double-adjacent Error Correcting Code (SDECC). Proposed codecs have been designed by employing new parity check matrices for different word lengths which are frequently applied in memory. The mis-correction probability of proposed SDECC codes are up to 88.24% and 80.67% lesser for 2-random and 3-random bit errors respectively with respect to related existing designs. Proposed codecs have been replicated and synthesized in ASIC environment. It is observed that area and power consumption of the proposed codecs are reduced up to 8.93% and 21.47% compared to the recently published results respectively.

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Authors and Affiliations

  1. Haldia Institute of Technology, Haldia, WB, 721657, India

    Raj Kumar Maity & Jagannath Samanta

  2. Jadavpur University, Kolkata, India

    Jaydeb Bhaumik

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  1. Raj Kumar Maity
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  2. Jagannath Samanta
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  3. Jaydeb Bhaumik
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Correspondence to Jagannath Samanta.

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Maity, R.K., Samanta, J. & Bhaumik, J. Single and double-adjacent error correcting code (SDECC) with lower design overheads and mis-correction rate for SRAMs. Microsyst Technol 29, 823–834 (2023). https://doi.org/10.1007/s00542-023-05464-3

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