Abstract
The article proposes a method for reducing the number of LUT elements in the circuit of a compositional microprogram control unit (CMCU) with code sharing. The method is based on the two-fold encoding of operator linear chains (OLC). Each chain has a code as an element of the OLC set and as a class element of this set. This approach allows obtaining a two-level microinstruction addressing unit. The control memory of the CMCU is implemented in the embedded memory blocks. The article considers an example of synthesis and provides an analysis of the proposed method.
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References
M. Kubica and D. Kania, “Technology mapping oriented to adaptive logic modules,” Bulletin of Polish Academy of Sci., Vol. 67, No. 5, 947–956 (2019).
V. Sklyarov, I. Skliarova, A. Barkalov, and L. Titarenko, Synthesis and Optimization of FPGA-Based Systems, Springer, Berlin (2014).
V. V. Solov’ev, Design of Digital Systems on the Basis of Programmable Logic Integrated Circuits [in Russian], Goryachaya Liniya-Telecom, Moscow (2001).
M. Rawski, P. Tomaszewicz, G. Borowski, and T. Luba, “Logic synthesis method of digital circuits designed for implementation with embedded memory blocks on FPGAs,” in: M. Adamski, A. Barkalov, and M. Wegrzyn (eds.), Design of Digital Systems and Devises; Lecture Notes in Electrical Engineering, Vol. 79, Springer, Berlin, (2011), pp. 121–144.
C. Maxfield, The Design Warrior’s Guide to FPGAs, Newnes, Amsterdam (2004).
I. Grout, Digital Systems Design with FPGAs and CPLDs, Elsevier, Amsterdam (2008).
M. Rawski, H. Selvaraj and T. Luba, “An application of functional decomposition in ROM-based FSM implementation in FPGA devices,” J. of System Architecture, Vol. 51, Iss. 6–7, 424–434 (2005).
R. Czerwinski and D. Kania, Finite State Machines Logic Synthesis for Complex Programmable Logic Devices; Lecture Notes in Electrical Engineering, Vol. 231, Springer Verlag, Berlin–Heidelberg (2013).
A. Mishchenko, S. Chattarejee, and R. Bryton, “Improvements to technology mapping for LUT-based FPGAs,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 2, 240–253 (2006).
S. Kilts, Advanced FPGA Design: Architecture, Implementation and Optimization, Willey-IEEE Press (2007).
A. A. Barkalov and L. A. Titarenko, Synthesis of Compositional Microprogram Control Units [in Russian], Kollehium, Kharkiv (2007).
A. A. Barkalov, L. A. Titarenko, and K. N. Efimenko, “Optimization of circuits of compositional microprogram control units implemented on FPGA,” Cybern. Syst. Analysis, Vol. 47, No. 1, 166–174 (2011). https://doi.org/10.1007/s10559-011-9299-1.
A. A. Barkalov and L. A. Titarenko, “Code conversion in compositional microprogram control units,” Cybern. Syst. Analysis, Vol. 47, No. 5, 763–772 (2011). https://doi.org/10.1007/s10559-011-9355-x.
White Paper FPGA Architecture. URL: www.altera.com.
A. Tiwari and K. Tomko, “Saving power by mapping finite state machines into embedded memory blocks in FPGAs,” in: Proc. Design, Automation and Test in Europe Conf. and Exhibition (Paris, France, 6–20 Feb 2004), Vol. 2 (2004), pp. 916–921.
C. Scholl, Functional Decomposition with Application to FPGA Synthesis, Kluwer Academic Publishers, Boston (2001).
M. Nowicka, T. Luba, and M. Rawski, “FPGA-based decomposition of Boolean functions: Algorithms and implementations,” in: Proc. of the 6th Intern. Conf. on Advanced Comput. Syst. (Szczecin, 1999), (1999), pp. 502–509.
A. Barkalov, L. Titarenko, and K. Mielcarek, “Hardware reduction for LUT-based Mealy FSMs,” Int. J. Appl. Math. Comput. Sci., Vol. 28, No. 3, 595–607 (2018).
S. Baranov, Logic Synthesis for Control Automata, Kluwer Academic Publishers, Dordrecht (1994).
A. Barkalov and L. Titarenko, Logic Synthesis for FSM-Based Control Units, Springer, Berlin (2009).
I. Kuon, R. Tessier, and J. Rose, “FPGA Architecture: Survey and challenges — found trends,” Foundations and Trends® in Electronic Design Automation, Vol. 2, No. 2, 135–253 (2008).
S. Yang, Logic Synthesis and Optimization Benchmarks User Guide, Version 3.0, Techn. Rep., Microelectronics Center of North Carolina (1991).
Vivado Design Suite. URL: https://www.xilinx.com/products/design-tools/vivado.html.
Intel® Quartus® Prime Software Suite. URL: https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html.
Virtex-7 FPGAs. URL: https://www.xilinx.com/products/silicon-devices/fpga/virtex-7.html.
A. Barkalov, L. Titarenko, and S. Chmielewski, “Mixed encoding of collections of output variables for LUT-based FSMs,” J. of Circuits, Syst. Comput., Vol. 28, No. 08, 1950131 (2019).
L. Garcia-Vargas and R. Senhaji-Navarro, “Finite state machines with input multiplexing: A performance study,” IEEE Trans. on CAD of Integrated Circuits and Systems, Vol. 34, Iss. 5, 867–871 (2015).
V. N. Opanasenko and S. L. Kryvyi, “Synthesis of neural-like networks on the basis of conversion of cyclic Hamming codes,” Cybern. Syst. Analysis, Vol. 53, No. 4, 627–635 (2017). https://doi.org/10.1007/s10559-017-9965-z.
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Translated from Kibernetyka ta Systemnyi Analiz, No. 5, September–October, 2021, pp. 22–34.
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Barkalov, A.A., Titarenko, L.A., Baiev, A.V. et al. Optimization of CMCU with Code Sharing. Cybern Syst Anal 57, 685–697 (2021). https://doi.org/10.1007/s10559-021-00394-2
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DOI: https://doi.org/10.1007/s10559-021-00394-2