Abstract
In the past several decades, the density and performance of transistors in a single chip have been increasing based on Moore’s Law. However, the slowdown of feature size reduction and memory wall in the von Neumann architecture restrict the improvement of system performance and energy efficiency. Thus the requirements of the emerging big data and artificial intelligence applications cannot be met. To address this issue, novel devices and architectures are being explored. Among them, the InGaZnO (IGZO) field-effect transistor (FET) device and the computing-in-memory (CIM) architecture can be possible solutions for high-density, high-performance, and high-efficiency applications. Herein, we review the recent progress in IGZO-based FETs for dynamic random access memory (DRAM) applications. The mechanism of IGZO FETs, compact modeling of IGZO transistors, progress of IGZO manufacturing process, IGZO circuit design, and IGZO-based CIM and 3D integration architectures are presented. Furthermore, the challenges and future trends of IGZO research are discussed.
Similar content being viewed by others
References
Kim S K, Popovici M. Future of dynamic random-access memory as main memory. MRS Bull, 2018, 43: 334–339
Chang M. Memory-2022 trends. In: Proceedings of IEEE International Solid-State Circuits Conference (ISSCC), 2022. 121–122
Chang J. Memory-2020 trends. In: Proceedings of IEEE International Solid-State Circuits Conference (ISSCC), 2020. 127–129
Mittal S, Inukonda M S. A survey of techniques for improving error-resilience of DRAM. J Syst Architecture, 2018, 91: 11–40
Lee J M, Park D S, Yew S, et al. Novel approach for the reduction of leakage current characteristics of 20 nm DRAM capacitors with ZrO2-based high-k dielectrics. IEEE Electron Dev Lett, 2017, 38: 1524–1527
Lee J M, Choi P H, Kim S K, et al. New method for reduction of the capacitor leakage failure rate without changing the capacitor structure or materials in DRAM mass production. IEEE Trans Electron Dev, 2018, 65: 4839–4845
Pešić M, Knebel S, Geyer M, et al. Low leakage ZrO2 based capacitors for sub 20 nm dynamic random access memory technology nodes. J Appl Phys, 2016, 119: 064101
Popovici M, Belmonte A, Oh H, et al. High-performance (EOT <0.4 nm, Jg ∼ 10−7 A/cm2) ALD-deposited RuSrTiO3 stack for next generations DRAM pillar capacitor. In: Proceedings of IEEE International Electron Devices Meeting, San Francisco, 2018. 51–54
Jang S, Lim J, Han J, et al. A fully integrated low voltage DRAM with thermally stable gate-first high-k metal gate process. In: Proceedings of IEEE International Electron Devices Meeting, San Francisco, 2019. 654–656
Okhonin S, Nagoga M, Sallese J M, et al. A capacitor-less 1T-DRAM cell. IEEE Electron Dev Lett, 2002, 23: 85–87
Song K W, Jeong H, Lee J W, et al. 55 nm capacitor-less 1T DRAM cell transistor with non-overlap structure. In: Proceedings of IEEE International Electron Devices Meeting, Washington D.C., 2008. 797
Navarro C, Karg S, Marquez C, et al. Capacitor-less dynamic random access memory based on a III–V transistor with a gate length of 14 nm. Nat Electron, 2019, 2: 412–419
Chun K C, Jain P, Kim T H, et al. A 1.1 V, 667 MHz random cycle, asymmetric 2T gain cell embedded DRAM with a 99.9 percentile retention time of 110 µsec. In: Proceedings of the 2010 Symposium on VLSI Technology and Circuits Digest of Technical Papers, Honolulu, 2010. 191–192
Li H, Lin Y. A 2T dual port capacitor-less DRAM. IEEE Electron Dev Lett, 2014, 35: 187–189
Oota M, Ando Y, Tsuda K, et al. 3D-stacked CAAC-In-Ga-Zn oxide FETs with gate length of 72 nm. In: Proceedings of IEEE International Electron Devices Meeting, San Francisco, 2019. 50–53
Ye H, Gomez J, Chakraborty W, et al. Double-gate W-doped amorphous indium oxide transistors for monolithic 3D capacitorless gain cell eDRAM. In: Proceedings of IEEE International Electron Devices Meeting, San Francisco, 2020. 613–616
Belmonte A, Oh H, Rassoul N, et al. Capacitor-less, long-retention (> 400 s) DRAM cell paving the way towards low-power and high-density monolithic 3D DRAM. In: Proceedings of IEEE International Electron Devices Meeting, San Francisco, 2020. 609–612
Nomura K, Ohta H, Takagi A, et al. Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors. Nature, 2004, 432: 488–492
Lee J H, Kim D H, Yang D J, et al. World’s largest (15-inch) XGA AMLCD panel using IGZO oxide TFT. In: Proceedings of Sid International Symposium, Digest of Technical Papers, 2008
Park J S, Kim T W, Stryakhilev D, et al. Flexible full color organic light-emitting diode display on polyimide plastic substrate driven by amorphous indium gallium zinc oxide thin-film transistors. Appl Phys Lett, 2009, 95: 013503
Kim B, Choi S, Kim B, et al. A novel level shifter employing IGZO TFT. IEEE Electron Dev Lett, 2011, 32: 167–169
Kamiya T, Nomura K, Hosono H. Present status of amorphous In−Ga−Zn−O thin-film transistors. Sci Tech Adv Mater, 2010, 11: 044305
Kimura M, Nakanishi T, Nomura K, et al. Trap densities in amorphous-InGaZnO4 thin-film transistors. Appl Phys Lett, 2008, 92: 133512
Lee W J, Park W T, Park S, et al. Large-scale precise printing of ultrathin sol-gel oxide dielectrics for directly patterned solution-processed metal oxide transistor arrays. Adv Mater, 2015, 27: 5043–5048
Sebastian A, Le Gallo M, Khaddam-Aljameh R, et al. Memory devices and applications for in-memory computing. Nat Nanotechnol, 2020, 15: 529–544
Si X, Chang M F, Khwa W S, et al. A dual-split 6T SRAM-based computing-in-memory unit-macro with fully parallel product-sum operation for binarized DNN edge processors. IEEE Trans Circ Syst I, 2019, 66: 4172–4185
Yu C, Yoo T, Kim H, et al. A logic-compatible eDRAM compute-in-memory with embedded ADCs for processing neural networks. IEEE Trans Circ Syst I, 2021, 68: 667–679
Shim W, Yu S. Technological design of 3D NAND-based compute-in-memory architecture for GB-scale deep neural network. IEEE Electron Dev Lett, 2021, 42: 160–163
Wan W E, Kubendran R, Eryilmaz S B, et al. A 74 TMACS/W CMOS-RRAM neurosynaptic core with dynamically reconfigurable dataflow and in-situ transposable weights for probabilistic graphical models. In: Proceedings of IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, 2020. 498–499
Sun X, Khwa W S, Chen Y S, et al. PCM-based analog compute-in-memory: impact of device non-idealities on inference accuracy. IEEE Trans Electron Dev, 2021, 68: 5585–5591
Jain S, Ranjan A, Roy K, et al. Computing in memory with spin-transfer torque magnetic RAM. IEEE Trans VLSI Syst, 2018, 26: 470–483
Hung J M, Li X, Wu J, et al. Challenges and trends indeveloping nonvolatile memory-enabled computing chips for intelligent edge devices. IEEE Trans Electron Dev, 2020, 67: 1444–1453
Zhang W, Gao B, Tang J, et al. Neuro-inspired computing chips. Nat Electron, 2020, 3: 371–382
Guo J, Han K, Subhechha S, et al. A new surface potential and physics based compact model for α-IGZO TFTs at multi-nanoscale for high retention and low-power DRAM application. In: Proceedings of IEEE International Electron Devices Meeting, San Francisco, 2021. 182–185
Guo J, Zhao Y, Yang G, et al. A new surface potential based compact model for independent dual gate α-IGZO TFT: experimental verification and circuit demonstration. In: Proceedings of IEEE International Electron Devices Meeting, San Francisco, 2020
Chasin A, Franco J, Triantopoulos K, et al. Understanding and modelling the PBTI reliability of thin-film IGZO transistors. In: Proceedings of IEEE International Electron Devices Meeting, San Francisco, 2021. 657–660
Guo J, Sun Y, Wang L, et al. Compact modeling of IGZO-based CAA-FETs with time-zero-instability and BTI impact on device and capacitor-less DRAM retention reliability. In: Proceedings of 2022 Symposium on VLSI Technology and Circuits Digest of Technical Papers, Honolulu, 2022. 300–301
Wu Z, Chasin A, Franco J, et al. Characterizing and modelling of the BTI reliability in IGZO-TFT using light-assisted I–V spectroscopy. In: Proceedings of IEEE International Electron Devices Meeting, San Francisco, 2022. 695–698
Kong Q, Liu G, Sun C, et al. New insights into the impact of hydrogen evolution on the reliability of IGZO FETs: experiment and modeling. In: Proceedings of IEEE International Electron Devices Meeting, San Francisco, 2022. 699–702
Belmonte A, Oh H, Subhechha S, et al. Tailoring IGZO-TFT architecture for capacitorless DRAM, demonstrating > 103 s retention, > 1011 cycles endurance and Lg scalability down to 14 nm. In: Proceedings of IEEE International Electron Devices Meeting, San Francisco, 2021. 226–228
Chen K, Niu J, Yang G, et al. Scaling dual-gate ultra-thin α-IGZO FET to 30 nm channel length with record-high Gm, max of 559 µS/µm at VDS = 1 V, record-low DIBL of 10 mV/V and nearly ideal SS of 63 mV/dec. In: Proceedings of 2022 Symposium on VLSI Technology and Circuits Digest of Technical Papers, Honolulu, 2022. 298–299
Lu W, Zhu Z, Chen K, et al. First demonstration of dual-gate IGZO 2T0C DRAM with novel read operation, one bit line in single cell, ION = 1500 µA/µm @ VDS = 1 V and Retention Time > 300 s. In: Proceedings of IEEE International Electron Devices Meeting, San Francisco, 2022. 611–614
Chand U, Fang Z, Chun-kuei C, et al. 2-kbit array of 3-D monolithically-stacked IGZO FETs with low SS-64 mV/dec, ultra-low-leakage, competitive μ ∼ 57cm2/V·s performance and novel nMOS-only circuit demonstration. In: Proceedings of 2021 Symposium on VLSI Technology and Circuits Digest of Technical Papers, 2021
Baba H, Ohshita S, Hamada T, et al. Novel analog in-memory compute with > 1 nA current/cell and 143.9 TOPS/W enabled by monolithic normally-off Zn-rich CAAC-IGZO FET-on-Si CMOS technology. In: Proceedings of IEEE International Electron Devices Meeting, San Francisco, 2021. 466–469
Biggs J, Myers J, Kufel J, et al. A natively flexible 32-bit arm microprocessor. Nature, 2021, 595: 532–536
Kunitake H, Ohshima K, Tsuda K, et al. High thermal tolerance of 25-nm c-axis aligned crystalline In−Ga−Zn oxide FET. In: Proceedings of IEEE International Electron Devices Meeting, San Francisco, 2018. 312–315
Mo F, Tagawa Y, Jin C, et al. Experimental demonstration of ferroelectric HfO2 FET with ultrathin-body IGZO for high-density and low-power memory application. In: Proceedings of 2019 Symposium on VLSI Technology and Circuits Digest of Technical Papers, Kyoto, 2019
Han K, Kong Q, Kang Y, et al. First demonstration of oxide semiconductor nanowire transistors: a novel digital etch technique, IGZO channel, nanowire width down to ∼20 nm, and Ion exceeding 1300 µA/µm. In: Proceedings of 2021 Symposium on VLSI Technology and Circuits Digest of Technical Papers, 2021
Sun C, Han K, Samanta S, et al. First demonstration of BEOL-compatible ferroelectric TCAM featuring α-IGZO Fe-TFTs with large memory window of 2.9 V, scaled channel length of 40 nm, and high endurance of 108 cycles. In: Proceedings of 2021 Symposium on VLSI Technology and Circuits Digest of Technical Papers, 2021
Samanta S, Han K, Sun C, et al. Amorphous IGZO TFTs featuring extremely-scaled channel thickness and 38 nm channel length: achieving record high Gm, max of 125 µS/µm at VDS of 1 V and ION of 350 µA/µm. In: Proceedings of 2020 Symposium on VLSI Technology and Circuits Digest of Technical Papers, 2020
Subhechha S, Rassoul N, Belmonte A, et al. First demonstration of sub-12 nm Lg gate last IGZO-TFTs with oxygen tunnel architecture for front gate devices. In: Proceedings of 2021 Symposium on VLSI Technology and Circuits Digest of Technical Papers, 2021
Subhechha S, Rassoul N, Belmonte A, et al. Ultra-low leakage IGZO-TFTs with raised source/drain for Vt > 0 V and Ion > 30 µA/µm. In: Proceedings of 2022 Symposium on VLSI Technology and Circuits Digest of Technical Papers, Honolulu, 2022
Wang C, Kumar A, Han K, et al. Extremely scaled bottom gate α-IGZO transistors using a novel patterning technique achieving record high Gm of 479.5 µS/µm (VDS of 1 V) and fT of 18.3 GHz (VDS of 3 V). In: Proceedings of 2022 Symposium on VLSI Technology and Circuits Digest of Technical Papers, Honolulu, 2022
Chang S W, Lu T H, Yang C Y, et al. First demonstration of heterogeneous IGZO/Si CFET monolithic 3D integration with dual workfunction gate for ultra low-power SRAM and RF applications. In: Proceedings of IEEE International Electron Devices Meeting, San Francisco, 2021. 733–736
Li Q J, Gu C, Zhu S, et al. BEOL-compatible high-performance α-IGZO transistors with record high Ids, max = 1207 µA/µm and on-off ratio exceeding 1011 at Vds = 1 V. In: Proceedings of IEEE International Electron Devices Meeting, San Francisco, 2022. 42–45
Duan X, Huang K, Feng J, et al. Novel vertical channel-all-around (CAA) IGZO FETs for 2T0C DRAM with high density beyond 4F2 by monolithic stacking. In: Proceedings of IEEE International Electron Devices Meeting, San Francisco, 2021. 222–225
Huang K, Duan X, Feng J, et al. Vertical channel-all-around (CAA) IGZO FET under 50 nm CD with high read current of 32.8 µA/µm (Vth + 1 V), well-performed thermal stability up to 120°C for low latency, high-density 2T0C 3D DRAM application. In: Proceedings of 2022 Symposium on VLSI Technology and Circuits Digest of Technical Papers, Honolulu, 2022. 296–297
Chen C, Duan X, Yang G, et al. Inter-layer dielectric engineering for monolithic stacking 4F2-2T0C DRAM with channel-all-around (CAA) IGZO FET to achieve good reliability (> 104 s bias stress, > 1012 cycles endurance. In: Proceedings of IEEE International Electron Devices Meeting, San Francisco, 2022. 615–618
Petti L, Münzenrieder N, Vogt C, et al. Metal oxide semiconductor thin-film transistors for flexible electronics. Appl Phys Rev, 2016, 3: 021303
Hu Q, Li Q, Zhu S, et al. Optimized IGZO FETs for capacitorless DRAM with retention of 10 ks at RT and 7 ks at 85°C at zero Vhold with sub-10 ns speed and 3-bit operation. In: Proceedings of IEEE International Electron Devices Meeting, San Francisco, 2022. 619–622
Cosemans S, Verhoef B, Doevenspeck J, et al. Towards 10000TOPS/W DNN inference with analog in-memory computing–a circuit blueprint, device options and requirements. In: Proceedings of IEEE International Electron Devices Meeting, San Francisco, 2019
Saito D, Doevenspeck J, Cosemans S, et al. IGZO-based compute cell for analog in-memory computing-DTCO analysis to enable ultralow-power AI at edge. IEEE Trans Electron Dev, 2020, 67: 4616–4620
Liu J, Tang W, Liu Y, et al. Almost-nonvolatile IGZO-TFT-based near-sensor in-memory computing. In: Proceedings of 2021 IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, 2021
Raman S, Xie S, Kulkarni J P. Compute-in-eDRAM with backend integrated indium gallium zinc oxide transistors. In: Proceedings of 2021 IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, 2021
Liu J L, Sun C, Tang W J, et al. Low-power and scalable retention-enhanced IGZO TFT eDRAM-based charge-domain computing. In: Proceedings of 2021 IEEE International Electron Devices Meeting (IEDM), San Francisco, 2021. 462–465
Bao L, Wang Z, Shi Y, et al. Experimental demonstration of high-order in-memory computing based on IGZO charge trapping RAM array for polynomial regression acceleration. In: Proceedings of IEEE International Electron Devices Meeting, San Francisco, 2022. 26–29
Spessot A, Oh H. 1T-1C dynamic random access memory status, challenges, and prospects. IEEE Trans Electron Dev, 2020, 67: 1382–1393
Shulaker M M, Hills G, Park R S, et al. Three-dimensional integration of nanotechnologies for computing and data storage on a single chip. Nature, 2017, 547: 74–78
Li Y, Tang J, Gao B, et al. Monolithic 3D integration of logic, memory and computing-in-memory for one-shot learning. In: Proceedings of IEEE International Electron Devices Meeting, San Francisco, 2021. 478–481
An R, Li Y, Tang J, et al. A hybrid computing-in-memory architecture by monolithic 3D integration of BEOL CNT/IGZO based CFET logic and analog RRAM. In: Proceedings of IEEE International Electron Devices Meeting, San Francisco, 2022. 419–422
Chen M C, Ohshita S, Amano S, et al. A > 64 multiple states and > 210 TOPS/W high efficient computing by monolithic Si/CAAC-IGZO + super-lattice ZrO2/Al2O3/ZrO2 for ultra-low power edge AI application. In: Proceedings of IEEE International Electron Devices Meeting, San Francisco, 2022. 423–426
Ozer E, Kufel J, Biggs J, et al. Malodour classification with low-cost flexible electronics. Nat Commun, 2023, 14: 777
Acknowledgements
This work was supported in part by National Key R&D Program (Grant No. 2018YFA0208503), National Natural Science Foundation of China (Grant Nos. 92264204, 61890944), and China Postdoctoral Science Foundation (Grant No. 2021M703444).
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Yan, S., Cong, Z., Lu, N. et al. Recent progress in InGaZnO FETs for high-density 2T0C DRAM applications. Sci. China Inf. Sci. 66, 200404 (2023). https://doi.org/10.1007/s11432-023-3802-8
Received:
Revised:
Accepted:
Published:
DOI: https://doi.org/10.1007/s11432-023-3802-8