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Optimization of circuits of compositional microprogram control units implemented on FPGA

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Cybernetics and Systems Analysis Aims and scope

Abstract

Two methods are proposed for microinstruction addressing in interpreting a control algorithm by a compositional microprogram control unit (CMCU). The method of refined addressing allows one to uniquely identify outputs of operational linear chains (OLCs) using a minimal number of address bits. The method of optimal addressing makes it possible to represent classes of pseudoequivalent OLCs using a minimal number of generalized intervals of the code space. The proposed methods are illustrated by examples. Both methods make it possible to reduce the number of look-up table (LUT) elements in a CMCU logic circuit in comparison with its base structure. In the majority of cases, the clock period decreases with decreasing the amount of hardware

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Authors and Affiliations

  1. University of Zielona Góra, Zielona Góra, Poland

    A. A. Barkalov & L. A. Titarenko

  2. Donetsk National Technical University, Donetsk, Ukraine

    K. N. Efimenko

Authors
  1. A. A. Barkalov
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  2. L. A. Titarenko
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  3. K. N. Efimenko
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Corresponding author

Correspondence to A. A. Barkalov.

Additional information

Translated from Kibernetika i Sistemnyi Analiz, No. 1, pp. 179–188, January–February 2011.

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Barkalov, A.A., Titarenko, L.A. & Efimenko, K.N. Optimization of circuits of compositional microprogram control units implemented on FPGA. Cybern Syst Anal 47, 166–174 (2011). https://doi.org/10.1007/s10559-011-9299-1

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  • DOI: https://doi.org/10.1007/s10559-011-9299-1

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