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Parametric analysis on DC and analog/linearity response of multi-channel FinFET (Mch-FinFET) with spacer engineering

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Abstract

A newly invented structure called Multi-Fin-based FinFET (M-FinFET) device is a promising candidate for future improvisation of the semiconductor industry. In this article, Multi-channel FinFET (Mch-FinFET) is proposed. A comparative investigation of various DC, analog/linearity attributes is studied for gate length variation and oxide thickness through a Sentaurus TCAD tool. The simulation study concluded that the increased number of channels (= 3no.) has enhanced ION by 409.71% compared to single-channel FinFET. The decreased value of Fin width and Fin height has shown an impressive improvement of sub-threshold swing (SS) and leakage current, which helps achieve a better switching ratio. Mch-FinFET device with lower oxide thickness (Tox=1 nm) enhances the transconductance (Gm), drain conductance (Gd), intrinsic gain (Av), and transconductance gain factor (TGF) by 52.42%, 41.17%, 85.03%, respectively. Various linearity parameters like higher-order harmonics (Gm2 and Gm3), voltage intercepts points (VIP2 and VIP3), and 1-dB compression point has improved by 32.32%, 110.71% 77%, 60.09%, 418.86%, 411.5% respectively gate length of 10 nm. Besides that, a symmetric dual spacer material is introduced to the proposed structure to analyze the importance of spacer engineering. The simulation study reveals that the Mch-FinFET device with HfO2 spacer has improved driving current by 21.42%. The optimization of various short channel effects (SCEs) such as threshold voltage roll-off, sub-threshold swing (SS), and leakage current is reflected in introducing HfO2 spacer material. This detailed study is expected to design low-power RF circuits that would benefit future CMOS technology.

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Acknowledgements

The authors would like to acknowledge Dr. Suman Kumar Mitra, Assistant professor, Department of Electronics Engineering, HBTU, Kanpur, India, for providing support. The authors also would like to acknowledge the National Institute of Technology, Agartala, India, for logistic support.

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  1. Department of Electronics and Communication Engineering, National Institute Of Technology Agartala, Tripura, 799046, India

    Rinku Rani Das & Atanu Chowdhury

  2. Department of Electrical and Electronics Engineering, Birla Institute of Technology and Science Pilani, Goa, 403726, India

    Apurba Chakraborty

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Corresponding Credit Author Statement: Rinku Rani Das: Methodology, simulation, paper writing Atanu Chowdhury: Discussions of simulation process Apurba Chakraborty: paper writing and rectification.

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Das, R.R., Chowdhury, A. & Chakraborty, A. Parametric analysis on DC and analog/linearity response of multi-channel FinFET (Mch-FinFET) with spacer engineering. Analog Integr Circ Sig Process 119, 1–13 (2024). https://doi.org/10.1007/s10470-023-02209-0

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