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Fin shape influence on analog and RF performance of junctionless accumulation-mode bulk FinFETs

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Abstract

The non-planar 3D structure of multi-gate FinFETs makes them able to be scaled down to 20 nm and beyond and also have greater performance. But any variation of the fin cross-sectional shape has an impact on the device performance. In this paper, the impact of various fin cross-sectional shape on junctionless accumulation mode bulk FinFETs with thin fins and short channel length has been evaluated. Different important device performance parameters such as ON-current (ION), OFF current (IOFF), ratio of ON/OFF current, Threshold voltage (Vth), Subthreshold swing (SS), drain-induced barrier lowering (DIBL), transconductance (gm), transconductance generation factor (gm/Ids), cut-off frequency (fT), and maximum oscillation frequency (fmax) is evaluated for different fin shapes and analyzed. From the analysis, it is understood that shape of the fin cross-section has substantial impact on performance of the device. Improvement in SCEs was noticed in terms of ~ 25% reduction of DIBL and ~ 10% reduction in SS for the device with reduced fin top width. On the other hand, reduced fin top width degrades the RF performance as maximum frequency of oscillation decrease by ~ 10%. An optimal fin structure for the junctionless bulk FinFET is also obtained to have better SCEs and reasonable Analog/RF applications.

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References

  • ATLAS (2011) ATLAS user manual. Silvaco Int., Santa Clara (online). http://www.silvaco.com

  • Choi JH, Kim TK, Moon JM, Yoon YG, Hwang BW, Kim DH, Lee S-H (2014) Origin of device performance enhancement of junctionless accumulation-mode (JAM) bulk FinFETs with high-κ gate spacers. IEEE Electron Device Lett 35(12):1182–1184

    Article  Google Scholar 

  • Colinge J-P et al (2010) Reduced electric field in junctionless transistors. Appl Phys Lett 96(7):073510

    Article  Google Scholar 

  • Crupi F, Alioto M, Franco J, Magnone P, Togo M, Horiguchi N, Groeseneken G (2012) Understanding the basic advantages of bulk FinFETs for sub- and near-threshold logic circuits from device measurements. In: IEEE transactions on circuits and systems—II: express briefs, vol 59, no 7

  • Doria RT et al (2011) Junctionless multiple-gate transistors for analog applications. IEEE Trans Electron Devices 58(8):2511–2519

    Article  Google Scholar 

  • Duarte JP, Paydavosi N, Venugopalan S, Sachid A, Hu C (2013) Unified FinFET compact model: modelling trapezoidal triple-gate FinFETs. In: International conference on simulation of semiconductor processes and devices (SISPAD), Glasgow, pp 135–138

  • Dubey Shashank, Kondekar Pravin N (2016) Fin shape dependent variability for strained SOI FinFETs. Microelectron Eng 162(16):63–68

    Article  Google Scholar 

  • Gaynor BD, Hassoun S (2014) Fin shape impact on FinFET leakage with application to multithreshold and ultralow-leakage FinFET design. IEEE Trans Electron Devices 61(8):2738–2744

    Article  Google Scholar 

  • Guin S, Sil M, Mallik A (2017) Comparison of logic performance of CMOS circuits implemented with junctionless and inversion-mode FinFETs. IEEE Trans Electron Devices 64(3):1366–1374

    Article  Google Scholar 

  • Ha D, Takeuchi H, Choi Y-K, King T-J (2004) Molybdenum gate technology for ultrathin-body MOSFETs and FinFETs. IEEE Trans Electron Devices 51(12):1989–2004

    Article  Google Scholar 

  • Hsu T-H, Lue H-T, Lai E-K, Hsieh J-Y, Wang Z-Y, Yang L-W, King Y-C, Yang T, Chen K-C,Hsieh K-Y, Liu R, Lu C-Y (2007) A high-speed BE-SONOS NAND flash utilizing the field enhancement effect of FinFET. In: IEDM technical digest, pp 913–916

  • Huang AP, Yang ZC, Chu PK (2010) Hafnium-based high-k gate dielectrics. In: Chu PK (ed) Advances in solid state circuit technologies, ISBN: 978-953-307-086-5

  • Jan CH et al (2012) A 22 nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications. In: 2012 International electron devices meeting, San Francisco, pp 3.1.1–3.1.4

  • Kim J, Huynh HA, Kim S (2017) Modeling of FinFET parasitic source/drain resistance with polygonal epitaxy. IEEE Trans Electron Devices 64(5):2072–2079

    Article  Google Scholar 

  • Lee C-W et al (2010) Low subthreshold slope in junctionless multigate transistors. Appl Phys Lett 96(10):102106

    Article  Google Scholar 

  • Manoj CR, Rao VR (2007) Impact of high-k gate dielectrics on the device and circuit performance of nanoscale FinFETs. IEEE Electron Device Lett 28(4):295–297

    Article  Google Scholar 

  • Md Rezali FA, Othman NAF, Mazhar M, Wan Muhamad Hatta S, Soin N (2016) Performance and device design based on geometry and process considerations for 14/16-nm strained FinFETs. IEEE Trans Electron Devices 63(3):974–981

    Article  Google Scholar 

  • Mohankumar N, Syamal B, Sarkar CK (2010) Influence of channel and gate engineering on the analog and RF performance of DG MOSFETs. IEEE Trans Electron Devices 57(4):820–826

    Article  Google Scholar 

  • Park T, Cho HJ, Chae JD, Han SY, Park D, Kim K, Yoon E, Lee JH (2006) Characteristics of the full CMOS SRAM cell using body-tied TG MOSFETs (bulk FinFETs). IEEE Trans Electron Devices 53(3):481–487

    Article  Google Scholar 

  • Raskin J-P, Chung TM, Kilchytska V, Lederer D, Flandre D (2006) Analog/RF performance of multiple gate SOI devices: wideband simulations and characterization. IEEE Trans Electron Devices 53(5):1088–1095

    Article  Google Scholar 

  • Rewari S, Nath V, Haldar S et al (2017) Hafnium oxide based cylindrical junctionless double surrounding gate (CJLDSG) MOSFET for high speed, high frequency digital and analog applications. Microsyst Technol. https://doi.org/10.1007/s00542-017-3436-3

    Google Scholar 

  • Rosner W, Landgraf E, Kretz J, Dreeskornfeld L, Schafer H, Stalele M, Schulz T, Hofmann F, Luyken RJ, Specht M, Hartwich J, Pamler W, Risch L (2004) Nanoscale FinFETs for low power applications. Solid-State Electron 48(10–11):1819–1823

    Article  Google Scholar 

  • Sachid AB, Chen M-C, Hu C (2016) FinFET with high-κ spacers for improved drive current. IEEE Electron Device Lett 37(7):835–838

    Article  Google Scholar 

  • Sahay S, Kumar MJ (2017) Diameter dependence of leakage current in nanowire junctionless field effect transistors. IEEE Trans Electron Devices 64(3):1330–1335

    Article  Google Scholar 

  • Seoane N et al (2016) Comparison of fin-edge roughness and metal grain work function variability in InGaAs and Si FinFETs. IEEE Trans Electron Devices 63(3):1209–1216

    Article  Google Scholar 

  • Sikarwar V, Khandelwal S, Akashe S (2013) Analysis and design of low power SRAM cell using independent gate FinFET. Radioelectron Commun Syst 56(9):434–440

    Article  Google Scholar 

  • Sung PJ et al (2017) High-performance uniaxial tensile strained n-channel JL SOI FETs and triangular JL bulk FinFETs for nanoscaled applications. IEEE Trans Electron Devices 64(5):2054–2060

    Article  MathSciNet  Google Scholar 

  • The International Technology Roadmap for Semiconductors (online). http://www.itrs.net

  • Trivedi N, Kumar M, Haldar S et al (2017) Assessment of analog RF performance for insulated shallow extension (ISE) cylindrical surrounding gate (CSG) MOSFET incorporating gate stack. Microsystem technology, pp 1–8. https://doi.org/10.1007/s00542-017-3456-z

  • Wang L et al (2014) 3D coupled electro-thermal FinFET simulations including the fin shape dependence of the thermal conductivity. In: International conference on simulation of semiconductor processes and devices (SISPAD), Yokohama, pp 269–272

  • Xu W, Yin H, Ma X, Hong P, Xu M, Meng L (2015) Novel 14-nm scallop-shaped FinFETs (S-FinFETs) on bulk-Si substrate. Nanoscale Res Lett 10(249):1–7

    Google Scholar 

  • Yu Z, Chang S, Wang H, He J, Huang Q (2015) Effects of Fin shape on sub-10 nm FinFETs. J Comput Electron 14(2):515–523

    Article  Google Scholar 

  • Zhang J, Si M, Lou XB, Wu W, Gordon RG, Ye PD (2015) InGaAs 3D MOSFETs with drastically different shapes formed by anisotropic wet etching. In: 2015 IEEE international electron devices meeting (IEDM), Washington, DC, pp 15.2.1–15.2.4

  • Zhang J, Si M, Lou XB, Wu W, Gordon RG, Ye PD (2015) InGaAs 3D MOSFETs with drastically different shapes formed by anisotropic wet etching. In: IEEE international electron devices meeting (IEDM)

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Authors and Affiliations

  1. ECE Department, MCKV Institute of Engineering, Liluah, WB, India

    Kalyan Biswas

  2. Kalyani Government Engineering College, Kalyani, WB, India

    Angsuman Sarkar

  3. Nano Device Simulation Laboratory, ETCE Department, Jadavpur University, Kolkata, WB, India

    Chandan Kumar Sarkar

Authors
  1. Kalyan Biswas
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  2. Angsuman Sarkar
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  3. Chandan Kumar Sarkar
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Correspondence to Kalyan Biswas.

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Biswas, K., Sarkar, A. & Sarkar, C.K. Fin shape influence on analog and RF performance of junctionless accumulation-mode bulk FinFETs. Microsyst Technol 24, 2317–2324 (2018). https://doi.org/10.1007/s00542-018-3729-1

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  • DOI: https://doi.org/10.1007/s00542-018-3729-1

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