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Effect of Positive/Negative Interface Trap Charges on the Performance of Multi Fin FinFET (M-FinFET)

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Abstract

Multiple Fins structured FinFET (M-FinFET) is a promising semiconductor device for future improvisation of CMOS technology. In this paper, we investigate the impact of interface trap charges (positive and negative trap) at the HfO2/Si interface in M-FinFET for the first time. The various important DC attributes, RF/analog, and linearity metrics are studied in presence and absence of traps. Simultaneously, the various trap concentration effect on the characteristics of M-FinFET are also observed. The results show that the introduction of interface trap charges (ITC) has optimized the ON current, OFF current, and also improves sub-threshold swing (SS) characteristics as compared to no trap condition. It is observed that negative trap having trap concentration of 1013/cm2 enhances the ION by 1.64%, SS by 5.66%, and various important RF/analog parameter such as transconductance frequency product (GFP) improves by 1.25%, device efficiency by 37.12% and intrinsic gain (Av) 90.38%. On the other hand, linearity parameters like VIP2, VIP3 and 1 dB compression point shows better performance in presence of positive and negative trap.

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Acknowledgments

The authors would like to acknowledge National Institute of Technology, Agartala, India, for logistic support.

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All authors contributed to the study conception and design.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, National Institute of Technology, Agartala, Tripura, 799046, India

    Rinku Rani Das & Atanu Chowdhury

  2. Department of Electronics and communication Engineering, Indian Institute of Engineering Science and Technology, Shibpur, 711103, India

    Santanu Maity

  3. Department of Electrical and Electronics Engineering, Birla Institute of Technology and Science, Pilani, Goa, 403726, India

    Apurba Chakraborty

  4. Department of Electrical and Electronics Engineering, Harcourt Butler Technical University, Kanpur, 208002, India

    Suman Kumar Mitra

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  1. Rinku Rani Das
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Das, R.R., Maity, S., Chowdhury, A. et al. Effect of Positive/Negative Interface Trap Charges on the Performance of Multi Fin FinFET (M-FinFET). Silicon 14, 8557–8566 (2022). https://doi.org/10.1007/s12633-022-01669-9

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