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Detailed implementation of asynchronous circuits on commercial FPGAs

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Abstract

This paper provides the essential details of implementing 4-phase bundled data and speed independent asynchronous circuits on FPGAs. The required Xilinx synthesis tools including attributes, constraints and hardware implementation of basic asynchronous elements like Cgate, delay line, and handshaking modules are discussed. Finally, two design and implementation examples of asynchronous circuits are introduced. In order to reduce area and energy overhead, an N-stage pipeline with internal loops is proposed and employed in asynchronous Fuzzy Logic Controller (FLC). It is observed that synchronous FLC operating at 100 MHz consumes 27% more dynamic power while occupying 23% fewer FPGA resources compared to its asynchronous counterpart. At the same time, the asynchronous circuit has obtained an improvement of 19% in FLC performance compared to synchronous FLC. The other implementation example explains the technical details of the design and implementation process of speed independent circuit using Petrify and ISE at the LUT level. Both design examples are implemented and tested successfully on FPGA board.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Schulich of Engineering, University of Calgary, Calgary, AB, Canada

    Ahmadreza Motaqi & Mohamed Helaoui

  2. Department of Electrical and Computer Engineering, Faculty of Shariaty, Tehran Branch, Technical and Vocational University (TVU), Tehran, Iran

    Soodeh AghliMoghaddam

  3. Department of Electrical Engineering, Iran University of Science and Technology, Narmak, Tehran, 16846-13114, Iran

    Mohammad Reza Mosavi

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  1. Ahmadreza Motaqi
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  2. Mohamed Helaoui
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  4. Mohammad Reza Mosavi
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Correspondence to Mohammad Reza Mosavi.

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Appendix

Appendix

See Table 4.

Table 4 Required ISE attributes and constraints for implementation of asynchronous circuits on FPGA
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Motaqi, A., Helaoui, M., AghliMoghaddam, S. et al. Detailed implementation of asynchronous circuits on commercial FPGAs. Analog Integr Circ Sig Process 103, 375–389 (2020). https://doi.org/10.1007/s10470-020-01602-3

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