Abstract
In this paper, a FPGA (Field Programmable Gate Array) based architecture for an area efficient asynchronous FIFO (First-In-First-Out) has been presented. There are various technologies, and algorithms are used for data transfer from one domain to another. First-In-First-Out method is the simplest of all. FIFO requires multiple asynchronous clocks to access the data. Asynchronous FIFO is important for safe data transfer. Data moves from one clock domain to another clock domain where both the domain frequencies are different. The calculation of memory depth has been presented based on read and write clock frequency; so that the FIFO works perfectly for specified frequency without data loss. In this proposed model of asynchronous FIFO, an area efficient FIFO architecture has been demonstrated, and this paper also provides the results obtained through VHDL (Very high-speed integrated circuit Hardware Description Language) simulation and FPGA implementation to demonstrate the reliability of the proposed model.
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Das, S., Basu, U., Das, R., Saha, S., Basu, A. (2022). FPGA Implementation of Asynchronous FIFO. In: Bhaumik, S., Chattopadhyay, S., Chattopadhyay, T., Bhattacharya, S. (eds) Proceedings of International Conference on Industrial Instrumentation and Control. Lecture Notes in Electrical Engineering, vol 815. Springer, Singapore. https://doi.org/10.1007/978-981-16-7011-4_39
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DOI: https://doi.org/10.1007/978-981-16-7011-4_39
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