Abstract
In this study, we propose an efficient, 1024 point, pipelined FFT processor based on the radix-2 decimation-in-frequency (R2DIF) algorithm using the single-path delay feedback (SDF) pipelined architecture. The proposed FFT processor is designed as an intellectual property (IP) logic core for easy integration into digital signal processing (DSP) systems. It employs the shift-add method to optimize the multiplication of twiddle factors instead of the dedicated, embedded functional blocks. The proposed design is implemented on a Xilinx Virtex-7 field programmable gate array (FPGA). The experimental results show that the proposed FFT design is more efficient in terms of speed, accuracy and resource utilization as compared to existing designs and hence more suitable for high-speed DSP applications.
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References
Cooley, J.W., Tukey, J.W.: An algorithm for the machine calculation of complex Fourier series. Math. Comput. 19, 297–301 (1965)
Sanchez, M.A., Garrido, M., Lopez-Vallejo, M., Grajal, J.: Implementing FFT-based digital channelized receivers on FPGA platforms. IEEE Trans. Aerosp. Electron. Syst. 44, 1567–1585 (2008)
Harikrishna, K., Rao, T.R., Labay, V.A.: FPGA implementation of FFT algorithm for IEEE 802.16 e (mobile WiMAX). Int. J. Comput. Theory Eng. 3, 197–203 (2011)
Chu, W., Champagne, B.: A noise-robust FFT-based auditory spectrum with application in audio classification. IEEE Tran. Audio Speech Lang. Process. 16, 137–150 (2008)
Pitkänen, T.O., Takala, J.: Low-power application-specific processor for FFT computations. J. Sig. Process. Syst. 63, 165–176 (2011)
Wang, Y., Tang, Y., Jiang, Y., Chung, J.-G., Song, S.-S., Lim, M.-S.: Novel memory reference reduction methods for FFT implementations on DSP processors. IEEE Trans. Sig. Process. 55, 2338–2349 (2007)
Derafshi, Z.H., Frounchi, J., Taghipour, H.: A high speed FPGA implementation of a 1024-point complex FFT processor. In: 2010 Second International Conference on Computer and Network Technology (ICCNT), pp. 312–315. IEEE (2010)
Iglesias, V., Grajal, J., Sanchez, M.A., López-Vallejo, M.: Implementation of a real-time spectrum analyzer on FPGA platforms. IEEE Trans. Instrum. Meas. 64, 338–355 (2015)
Zhou, B., Peng, Y., Hwang, D.: Pipeline FFT architectures optimized for FPGAs. Int. J. Reconfigurable Comput. 2009, 1–9 (2009)
Garrido, M., Parhi, K.K., Grajal, J.: A pipelined FFT architecture for real-valued signals. IEEE Trans. Circ. Syst. I: Regul. Pap. 56, 2634–2643 (2009)
Wang, Z., Liu, X., He, B., Yu, F.: A combined SDC-SDF architecture for normal I/O pipelined Radix-2 FFT. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 23, 973–977 (2015)
Ma, Z.-G., Yin, X.-B., Yu, F.: A novel memory-based FFT architecture for real-valued signals based on a Radix-2 decimation-in-frequency algorithm. IEEE Trans. Circ. Syst. II: Exp. Briefs 62, 876–880 (2015)
Luo, H.-F., Liu, Y.-J., Shieh, M.-D.: Efficient memory-addressing algorithms for FFT processor design. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 23, 2162–2172 (2015)
Joshi, S.M.: FFT architectures: a review. Int. J. Comput. Appl. 116, 1–5 (2015)
Kumar, M., Selvakumar, A., Sobha, P.: Area and frequency optimized 1024 point Radix-2 FFT processor on FPGA. In: 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA), pp. 1–6. IEEE (2015)
Xilinx, Inc.: Logic core IP Fast Fourier Transform v8.0, Product specifications DS808 (2012)
Acknowledgments
This work was supported by the Korea Institute of Energy Technology Evaluation and Planning(KETEP) and the Ministry of Trade, Industry & Energy (MOTIE) of the Republic of Korea (No. 20161120100350, No. 20162220100050), in part by The Leading Human Resource Training Program of Regional Neo industry through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT and future Planning (NRF-2016H1D5A1910564), in part by Business for Cooperative R&D between Industry, Academy, and Research Institute funded Korea Small and Medium Business Administration in 2016 (Grants No. C0395147, Grants S2381631), and in part by the development of a basic fusion technology in electric power industry (Ministry of Trade, Industry & Energy, 201301010170D).
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Nguyen, NH., Khan, S.A., Kim, CH., Kim, JM. (2017). An FPGA-Based Implementation of a Pipelined FFT Processor for High-Speed Signal Processing Applications. In: Wong, S., Beck, A., Bertels, K., Carro, L. (eds) Applied Reconfigurable Computing. ARC 2017. Lecture Notes in Computer Science(), vol 10216. Springer, Cham. https://doi.org/10.1007/978-3-319-56258-2_8
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DOI: https://doi.org/10.1007/978-3-319-56258-2_8
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