Abstract
This work proposes a four-channel time-interleaved 11 b 150 MS/s pipelined SAR ADC based on various analog techniques to minimize mismatches between channels without any calibration scheme. The proposed ADC eliminates an input SHA to reduce offset mismatches, while the pipelined SAR architecture solves the problem of limited input bandwidth as observed in conventional SHA-free ADCs. In addition, a shared residue amplifier between four channels minimizes various mismatches caused by amplifiers in the first-stage MDACs. Two types of references for the residue amplifier and the SAR ADCs isolate the reference instability problem due to different functional requirements, while the shared residue amplifier uses only a single reference during the amplifying mode of each channel to reduce a gain mismatch. For high performance of the SAR ADC, high-frequency clocks with a controllable duty cycle are generated on chip without external, complicated, high-speed multi-phase clocks. The prototype 11 b ADC in a 0.13 μm CMOS shows a measured DNL and INL of 0.31 LSB and 1.18 LSB, respectively, with an SNDR of 59.3 dB and an SFDR of 67.7 dB at 100 MS/s, and an SNDR of 54.5 dB and an SFDR of 65.5 dB at 150 MS/s. The ADC with an active die area of 2.42 mm2 consumes 46.8 mW at 1.2 V and 150 MS/s.
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Acknowledgments
This work was supported by the IDEC of KAIST, the MSIP (Ministry of Science, ICT & Future Planning), Korea, under the University ITRC support program (NIPA-2013-H0301-13-1007) supervised by the NIPA (National IT Industry Promotion Agency), and the Basic Science Research Program through the National Research Foundation (NRF) funded by the Ministry of Education, Science and Technology (2012-0002297).
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Appendices
Appendix 1
To confirm the effect of offset mismatch between channels in the T-I ADC, Appendix 1 derives the SNDR of the overall ADC based on [17] when a different offset in each of the four channels (i.e., OS1, OS2, OS3 and OS4) exists, respectively. In addition, an analysis process and the definition of NQ1, OS13, OS24, OSd, OSc are summarized in detail.
When the input signal of (1) is sampled, the output of the four-channel T-I ADC is defined as (5) considering the offset of each channel.
The output is derived as (6).
Here,
The averaged quantization noise, NQ1, in the four channels is expressed as (7) with a resolution of N bits.
Here,
Therefore, the final SNDR is defined as (8) considering the quantization noise, NQ1.
Appendix 2
To confirm the effect of gain mismatch between channels in the T-I ADC, Appendix 2 derives the SNDR of the overall ADC based on [17] when a different gain in each of the four channels (i.e., G1, G2, G3 and G4) exists, respectively. In addition, an analysis process and the definition of NQ2, G13, G24, Gd, Gc are summarized in detail.
When the input signal of (1) is sampled, the output of the four-channel T-I ADC is defined as (9) considering the gain mismatch of each channel.
The output is derived as (10).
Here,
The averaged quantization noise, NQ2, in the four channels is expressed as (11) with a resolution of N bits.
Here,
Therefore, the final SNDR is defined as (12) considering the quantization noise, NQ2.
Appendix 3
To confirm the effect of sampling time mismatch between channels in the T-I ADC, Appendix 3 derives the SNDR of the overall ADC based on [17] when a sampling time error (i.e., θ1, θ2, θ3 and θ4) exists in each of the four channels, respectively. In addition, an analysis process and the definition of NQ3, θ13a, θ13b, θ24a, θ24b, θd1, θd2, θc1, θc2 are summarized in detail.
When the input signal of (1) is sampled, the output of the four-channel T-I ADC is defined as (13) considering the sampling time mismatch of each channel.
The output is derived as (14).
Here,
The averaged quantization noise, NQ3, in the four channels is expressed as (15) with a resolution of N bits.
Here,
Therefore, the final SNDR is defined as (16) considering the quantization noise, NQ3.
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Park, HL., Choi, MH., Nam, SP. et al. A mismatch-error minimized four-channel time-interleaved 11 b 150 MS/s pipelined SAR ADC. Analog Integr Circ Sig Process 76, 1–13 (2013). https://doi.org/10.1007/s10470-013-0074-2
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DOI: https://doi.org/10.1007/s10470-013-0074-2