Abstract
An ADC featuring a new architecture for an 8 b 64× interleaved CMOS ADC running at up to 100 GHz sampling frequency is presented. The ADC fulfills all specifications for 100 Gb/s ITU-OTU4 communication over long-distance optical fiber channels. It is based on a SAR ADC, known for its superior energy efficiency and suitability for deep-submicron digital CMOS processes, as the comparator is the only true analog element. Several improvements to existing SAR ADC architectures are presented. Alternate comparators are used to increase the sampling speed at no power and area penalty, and dynamic memory is used to reduce latency in the CDAC feedback. A deep-trench capacitor-based reference buffer significantly reduces power at low output impedance, and a differential CDAC with constant common mode and fractional reference voltages optimizes comparator performance and silicon area. The 64× interleaved ADC consists of a dedicated sampling and interleaving block and 64 SAR ADCs. Four interleaved passive samplers based on a sampling switch with in-line 1:4 demultiplexer provide an initial 1:16 interleaving with high linearity and more than 20 GHz input bandwidth while using only a single supply voltage.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Optical Interconnect Forum, “OIF-SFI-S-01.0. scalable SERDES framer interface (SFI-S): Implementation agreement of interfaces beyond 40G for physical layer devices,” http://www.oiforum.com/public/documents/OIF_SFI-S_01.0_IA.pdf, 2008.
C. Malouin, B. Zhang, A. Wagner, S. Khatana, E. Ibragimov, H. Jiang, and T. Schmidt, “Sub-rate sampling in 100 Gb/s coherent optical receivers,” OFC/NFOEC, pp. 1–3, Mar. 2010.
Y. Greshishchev, Nyquist AD Converters, Sensor Interfaces, and Robustness. Springer, 2012, ch. 6 CMOS ADCs for Optical Communications.
L. Kull, T. Toifl, M. Schmatz, P. A. Francese, C. Menolfi, M. Brändli, M. Kossel, T. Morf, T. M. Andersen, and Y. Leblebici, “A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32 nm digital SOI CMOS,” in ISSCC Dig. Tech. Papers, Feb. 2013, pp. 468–469.
L. Kull, T. Toifl, M. Schmatz, P. A. Francese, C. Menolfi, M. Brändli, M. Kossel, T. Morf, T. M. Andersen, and Y. Leblebici, “A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32 nm digital SOI CMOS,” IEEE J. Solid-State Circuits, vol. 48, no. 12, pp. 3049–3058, Dec. 2013.
C.-C. Liu, Y.-T. Huang, G.-Y. Huang, S.-J. Chang, C.-M. Huang, and C.-H. Huang, “A 6-bit 220-MS/s time-interleaving SAR ADC in 0.18-m digital CMOS process,” in Proc. International Symposium on VLSI Design, Automation and Test, Apr. 2009, pp. 215–218.
B. Jayaraman, S. Gupta, Y. Zhang, P. Goyal, H. Ho, R. Krishnan, S. Fang, S. Lee, D. Daley, K. McStay, B. Wunder, J. Barth, S. Deshpande, P. Parries, R. Malik, P. Agnello, S. Stiffler, and S. S. Iyer, “Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond,” in Proc. IEEE International Conference on IC Design & Technology (ICICDT), May 2012, pp. 1–4.
T. Kobayashi, K. Nogami, T. Shirotori, and Y. Fujimoto, “A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture,” IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 523–527, Apr. 1993.
M. Miyahara, Y. Asada, D. Paik, and A. Matsuzawa, “A low-noise self-calibrating dynamic comparator for high-speed ADCs,” in IEEE Proc. Asian Solid-State Circuit Conf., November 2008, pp. 269–272.
P. Nuzzo, F. D. Bernardinis, P. Terreni, and G. V. der Plas, “Noise analysis of regenerative comparators for reconfigurable ADC architectures,” IEEE Trans. on Circuits and Systems II, vol. 55, no. 6, pp. 1441–1454, July 2008.
B. Wicht, T. Nirschl, and D. Schmitt-Landsiedel, “Yield and speed optimization of a latch-type voltage sense amplifier,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1148–1158, July 2004.
L. Kull, T. Toifl, M. Schmatz, P. A. Francese, C. Menolfi, M. Brändli, M. Kossel, T. Morf, T. M. Andersen, and Y. Leblebici, “A 90GS/s 8b 667mW 64 interleaved SAR ADC in 32 nm digital SOI CMOS,” in ISSCC Dig. Tech. Papers, Feb. 2014, pp. 378–379.
B. Murmann, “ADC performance survey 1997-2013,” http://www.stanford.edu/~murmann/adcsurvey.html, 2013.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2015 Springer International Publishing Switzerland
About this chapter
Cite this chapter
Kull, L. et al. (2015). Energy-Efficient High-Speed SAR ADCs in CMOS. In: Harpe, P., Baschirotto, A., Makinwa, K. (eds) High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-319-07938-7_3
Download citation
DOI: https://doi.org/10.1007/978-3-319-07938-7_3
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-07937-0
Online ISBN: 978-3-319-07938-7
eBook Packages: EngineeringEngineering (R0)