Skip to main content
Log in

Germanium-source L-shaped TFET with dual in-line tunneling junction

  • Published:
Applied Physics A Aims and scope Submit manuscript

Abstract

In this paper, we propose a Si/Ge heterojunction TFET with two in-line tunneling junctions to enhance the low on-state current of TFETs, which is their main drawback. The device, named GL-TFET, has an L-shaped architecture with two bottom and side Ge-source regions and an S-shaped gate to enhance the electric field in the device channel. Tunneling of electrons happens in two vertical and horizontal directions from bottom source and side source, respectively, both perpendicular to the gate, and leads to a remarkably high on-state current of 569µA/µm at 0.5 V operating voltage, which is a new record. Our TFET shows sub-60 mV/dec point subthreshold swing over 10 decades of drain current and average subthreshold swing of 11.6 mV/dec, while owing to its geometrical design, no ambipolar conduction is observed in the transfer characteristics. In addition to the switching performance of the proposed device, the analog and RF characteristics are also investigated and a cut-off frequency of 148 GHz is recorded. The performance evaluation is carried out using a calibrated numerical device simulator.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6

source region

Fig. 7

source region a, and doping concentration of channel region b, on the transfer characteristics of the device

Fig. 8
Fig. 9
Fig. 10
Fig. 11

Similar content being viewed by others

References

  1. D. Mohata, S. Mookerjea, A. Agrawal, Y. Li, T. Mayer, V. Narayanan, A. Liu, D. Loubychev, J. Fastenau, S. Datta, Experimental staggered-source and N+ pocket-doped channel III–V tunnel field-effect transistors and their scalabilities. Appl. Phys. Express 4(2), 024105 (2011). https://doi.org/10.1143/APEX.4.024105

    Article  ADS  Google Scholar 

  2. T. Krishnamohan, D. Kim, S. Raghunathan, and K. Saraswat, (2008) Double-gate strained-Ge heterostructure tunneling FET (TFET) with record high drive currents and≪ 60mV/dec subthreshold slope," In 2008 IEEE International Electron Devices Meeting, 1–3. https://doi.org/10.1109/IEDM.2008.4796839

  3. K. Boucart, A.M. Ionescu, Double-gate tunnel FET with high-$\kappa $ gate dielectric. IEEE Trans. Electron Devices 54(7), 1725–1733 (2007). https://doi.org/10.1109/TED.2007.899389

    Article  ADS  Google Scholar 

  4. L. Lattanzio, L. De. Michielis, A.M. Ionescu, The electron–hole bilayer tunnel FET. Solid-State Electron. 74, 85–90 (2012). https://doi.org/10.1016/j.sse.2012.04.016

    Article  ADS  Google Scholar 

  5. H.M. Fahad, M.M. Hussain, High-performance silicon nanotube tunneling FET for ultralow-power logic applications. IEEE Trans. Electron Devices 60(3), 1034–1039 (2013). https://doi.org/10.1109/TED.2013.2243151

    Article  ADS  Google Scholar 

  6. L. De. Michielis, L. Lattanzio, K.E. Moselund, H. Riel, A.M. Ionescu, Tunneling and occupancy probabilities: how do they affect tunnel-FET behavior? IEEE Electron Device Lett. 34(6), 726–728 (2013). https://doi.org/10.1109/LED.2013.2257665

    Article  ADS  Google Scholar 

  7. M. Luisier, G. Klimeck, Simulation of nanowire tunneling transistors: From the Wentzel–Kramers–Brillouin approximation to full-band phonon-assisted tunneling. J. Appl. Phys. 107(8), 084507 (2010). https://doi.org/10.1063/1.3386521

    Article  ADS  Google Scholar 

  8. G. Dewey, B. Chu-Kung, J. Boardman, J. Fastenau, J. Kavalieros, R. Kotlyar, W. Liu, D. Lubyshev, M. Metz, and N. Mukherjee, (2011) Fabrication, characterization, and physics of III–V heterojunction tunneling field effect transistors (H-TFET) for steep sub-threshold swing, In 2011 International electron devices meeting, 2011, 33.6. 1–33.6.4. https://doi.org/10.1109/IEDM.2011.6131666

  9. S. Mookerjea, D. Mohata, R. Krishnan, J. Singh, A. Vallett, A. Ali, T. Mayer, V. Narayanan, D. Schlom, and A. Liu, (2009) Experimental demonstration of 100nm channel length In 0.53 Ga 0.47 As-based vertical inter-band tunnel field effect transistors (TFETs) for ultra low-power logic and SRAM applications, In: 2009 IEEE international electron devices meeting (IEDM), 1–3. https://doi.org/10.1109/IEDM.2009.5424355

  10. R. Kotlyar, U. Avci, S. Cea, R. Rios, T. Linton, K. Kuhn, I. Young, Bandgap engineering of group IV materials for complementary n and p tunneling field effect transistors. Appl. Phys. Lett. 102(11), 113106 (2013). https://doi.org/10.1063/1.4798283

    Article  ADS  Google Scholar 

  11. J. Knoch, J. Appenzeller, Modeling of high-performance p-type III–V heterojunction tunnel FETs. IEEE Electron Device Lett. 31(4), 305–307 (2010). https://doi.org/10.1109/LED.2010.2041180

    Article  ADS  Google Scholar 

  12. S.H. Kim, S. Agarwal, Z.A. Jacobson, P. Matheu, C. Hu, T.J.K. Liu, Tunnel field effect transistor with raised germanium source. IEEE Electron Device Lett. 31(10), 1107–1109 (2010). https://doi.org/10.1109/LED.2010.2061214

    Article  ADS  Google Scholar 

  13. S. H. Kim, H. Kam, C. Hu, and T. J. K. Liu, (2009) Ge-source tunnel field effect transistors with record high ION/IOFF, VLSI Symposium Technical Digest, 178–179. https://ieeexplore.ieee.org/document/5200679

  14. W. Wang, P. Wang, C. Zhang, X. Lin, X. Liu, Q.-Q. Sun, P. Zhou, D.W. Zhang, Design of U-shape channel tunnel FETs with SiGe source regions. IEEE Trans. Electron Devices 61(1), 193–197 (2014). https://doi.org/10.1109/TED.2013.2289075

    Article  ADS  Google Scholar 

  15. Z. Yang, Tunnel field-effect transistor with an L-shaped gate. IEEE Electron Device Lett. 37(7), 839–842 (2016). https://doi.org/10.1109/LED.2016.2574821

    Article  ADS  Google Scholar 

  16. N. Bagga, A. Kumar, S. Dasgupta, Demonstration of a novel two source region tunnel FET. IEEE Trans. Electron Devices 64(12), 5256–5262 (2017). https://doi.org/10.1109/TED.2017.2759898

    Article  ADS  Google Scholar 

  17. S. Chen, S. Wang, H. Liu, W. Li, Q. Wang, X. Wang, Symmetric U-shaped gate tunnel field-effect transistor. IEEE Trans. Electron Devices 64(3), 1343–1349 (2017). https://doi.org/10.1109/TED.2017.2647809

    Article  ADS  Google Scholar 

  18. P.-C. Shih, W.-C. Hou, J.-Y. Li, A U-Gate InGaAs/GaAsSb heterojunction TFET of tunneling normal to the gate with separate control over ON- and OFF-state Current. IEEE Electron Device Lett. 38(12), 1751–1754 (2017). https://doi.org/10.1109/LED.2017.2759303

    Article  ADS  Google Scholar 

  19. R.M. Imenabadi, M. Saremi, W.G. Vandenberghe, A novel PNPN-like Z-shaped tunnel field-effect transistor with improved ambipolar behavior and RF performance. IEEE Trans. Electron Devices 64(11), 4752–4758 (2017). https://doi.org/10.1109/TED.2017.2755507

    Article  ADS  Google Scholar 

  20. Silvaco, (2015) ATLAS Device Simulation Software User’s Manual, no. version 3.2., https://doi.org/10.13155/29825.

  21. F.S. Neves, P.G. Agopian, J.A. Martino, B. Cretu, R. Rooyackers, A. Vandooren, E. Simoen, A.V.Y. Thean, C. Claeys, Low-frequency noise analysis and modeling in vertical tunnel FETs with Ge source. IEEE Trans. Electron Devices 63(4), 1658–1665 (2016). https://doi.org/10.1109/TED.2016.2533360

    Article  ADS  Google Scholar 

  22. K.-H. Kao, A.S. Verhulst, W.G. Vandenberghe, B. Soree, G. Groeseneken, K. De. Meyer, Direct and indirect band-to-band tunneling in germanium-based TFETs. IEEE Trans. Electron Devices 59(2), 292–301 (2011). https://doi.org/10.1109/TED.2011.2175228

    Article  ADS  Google Scholar 

  23. C. Alper, L. Lattanzio, L. De. Michielis, P. Palestri, L. Selmi, A.M. Ionescu, Quantum mechanical study of the germanium electron–hole bilayer tunnel FET. IEEE Trans. Electron Devices 60(9), 2754–2760 (2013). https://doi.org/10.1109/TED.2013.2274198

    Article  ADS  Google Scholar 

  24. D. Querlioz, J. Saint-Martin, K. Huet, A. Bournel, V. Aubry-Fortuna, C. Chassat, S. Galdin-Retailleau, P. Dollfus, On the ability of the particle Monte Carlo technique to include quantum effects in nano-MOSFET simulation. IEEE Trans. Electron Devices 54(9), 2232–2242 (2007). https://doi.org/10.1109/TED.2007.902713

    Article  ADS  Google Scholar 

  25. A. Acharya, A. Solanki, S. Glass, Q.-T. Zhao, B. Anand, Impact of gate-source overlap on the device/circuit analog performance of line TFETs. IEEE Trans. Electron Devices 66(9), 4081–4086 (2019). https://doi.org/10.1109/TED.2019.2927001

    Article  ADS  Google Scholar 

  26. S.W. Kim, J.H. Kim, T.K. Liu, W.Y. Choi, B. Park, Demonstration of L-shaped tunnel field-effect transistors. IEEE Trans. Electron Devices 63(4), 1774–1778 (2016). https://doi.org/10.1109/TED.2015.2472496

    Article  ADS  Google Scholar 

  27. P.-Y. Wang, B.-Y. Tsui, Investigation into gate-to-source capacitance induced by highly efficient band-to-band tunneling in p-channel Ge epitaxial tunnel layer tunnel FET. IEEE Trans. Electron Devices 63(4), 1788–1790 (2016). https://doi.org/10.1109/TED.2016.2535373

    Article  ADS  Google Scholar 

  28. X. Duan, J. Zhang, S. Wang, Y. Li, S. Xu, Y. Hao, A high-performance gate engineered InGaN dopingless tunnel FET. IEEE Trans. Electron Devices 65(3), 1223–1229 (2018). https://doi.org/10.1109/TED.2018.2796848

    Article  ADS  Google Scholar 

  29. S. Tirkey, B.R. Raad, A. Gedam, D. Sharma, Junction-less charge plasma TFET with dual drain work functionality for suppressing ambipolar nature and improving radio-frequency performance. Micro Nano Lett 13(1), 18–23 (2018). https://doi.org/10.1049/mnl.2017.0197

    Article  Google Scholar 

  30. A. Acharya, A.B. Solanki, S. Dasgupta, B. Anand, Drain current saturation in line tunneling-based TFETs: an analog design perspective. IEEE Trans. Electron Devices 65(1), 322–330 (2017). https://doi.org/10.1109/TED.2017.2771249

    Article  ADS  Google Scholar 

  31. M.R. Tripathy, A.K. Singh, K. Baral, P.K. Singh, S. Jit, III-V/Si staggered heterojunction based source-pocket engineered vertical TFETs for low power applications. Superlattices. Microstruct. 142, 106494 (2020). https://doi.org/10.1016/j.spmi.2020.106494

    Article  Google Scholar 

  32. C. Pandey, A. Singh, S. Chaudhury, Effect of asymmetric gate–drain overlap on ambipolar behavior of double-gate TFET and its impact on HF performances. Appl. Phys. A 126(3), 1–12 (2020). https://doi.org/10.1007/s00339-020-3402-2

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Saeed Mohammadi.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Chahardah Cherik, I., Mohammadi, S. Germanium-source L-shaped TFET with dual in-line tunneling junction. Appl. Phys. A 127, 525 (2021). https://doi.org/10.1007/s00339-021-04677-5

Download citation

  • Received:

  • Accepted:

  • Published:

  • DOI: https://doi.org/10.1007/s00339-021-04677-5

Keywords

Navigation