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Ambipolarity Suppression of Band Gap and Gate Dielectric Engineered Novel Si0.2Ge0.8/GaAs JLTFET Using Gate Overlap Technique

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Abstract

This paper presents a dual dielectric gate-gate overlap hetero-structure junctionless tunnel field effect transistor (DDG-GOHJLTFET), in which first time, a combined effort of the band gap, gate overlap, and gate dielectric engineering is applied to novel composition Si1-xGex/GaAs for the purpose to suppress ambipolar current (IAmb) and improve the electrical characteristics of the device. The use of gate overlap engineering with GaAs material at the drain/channel (Dr/Ch) interface suppresses the IAmb, while the use of gate dielectric engineering along with Si1-xGex/GaAs at the source/channel (So/Ch) interface enhances the electrical characteristics of the device. In terms of DC characteristics, DDG-GOHJLTFET exhibits superior performance to the conventional Si-JLTFET by providing 1.2 × 103 times improved ION (1.1 × 10–7 A/μm to 1.36 × 104 A/μm), 7 × 109 times greater ION/IAmb ratio (3.5 × 104 μA/μA to 2.4 × 1014 μA/μA) and 79% reduced SS (147 mV/dec to 30.8 mV/dec). Further, the analog/RF parameters of the proposed device have been investigated. DDG-GOHJLTFET provides 8.2 × 102, 1.6 × 103, and 4.3 × 102 times higher gm (0.7 μS to 576 μS), fT (2.27 × 109 Hz to 3.62 × 1012 Hz), and fmax (4.28 × 108 Hz to 1.82 × 1011 Hz) compared to Si-JLTFET respectively, which shows the appropriateness of the proposed device for RF applications. Additionally, we examine three linearity characteristics, including gm2, gm3, and VIP2, and our results show that the proposed device performs better in terms of linearity.

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References

  1. Lu H, Seabaugh A (2014) Tunnel field-effect transistors: state-of-the-art. IEEE J Electron Devices Soc 2:44–49. https://doi.org/10.1109/JEDS.2014.2326622

    Article  Google Scholar 

  2. Leung G, Chui CO (2013) Stochastic variability in silicon double-gate lateral tunnel field-effect transistors. IEEE Trans Electron Devices 60:84–91. https://doi.org/10.1109/TED.2012.2226725

    Article  Google Scholar 

  3. Talukdar J, Rawat G, Mummaneni K (2020) A novel extended source TFET with δp+- SiGe layer. Silicon 12:2273–2281. https://doi.org/10.1007/s12633-019-00321-3

    Article  CAS  Google Scholar 

  4. Kim JH, Kim S, Park BG (2019) Double-gate TFET with vertical channel sandwiched by lightly doped Si. IEEE Trans Electron Devices 66:1656–1661. https://doi.org/10.1109/TED.2019.2899206

    Article  CAS  Google Scholar 

  5. Chen S, Wang S, Liu H et al (2020) A novel dopingless fin-shaped SiGe channel TFET with improved performance. Nanoscale Res Lett 15:202. https://doi.org/10.1186/S11671-020-03429-3

    Article  CAS  PubMed  PubMed Central  Google Scholar 

  6. Shekhar S, Madan J, Chaujar R (2018) Source/gate material-engineered double gate TFET for improved RF and linearity performance: a numerical simulation. Appl Phys A Mater Sci Process 124:1–10. https://doi.org/10.1007/s00339-018-2158-4

    Article  CAS  Google Scholar 

  7. Kumar K, Kumar A, Kumar V, Sharma SC (2023) Comparative investigation of band gap and gate metal engineered novel Si0.2Ge0.8/GaAs charge plasma-based JLTFET for improved electrical performance. Silicon. https://doi.org/10.1007/s12633-023-02387-6

    Article  Google Scholar 

  8. Mishra V, Verma YK, Gupta SK, Rathi V (2021) A SiGe-source doping-less double-gate tunnel FET: design and analysis based on charge plasma technique with enhanced performance. Silicon 145(14):2275–2282. https://doi.org/10.1007/S12633-021-01030-6

    Article  Google Scholar 

  9. Panda S, Dash S (2022) Drain dielectric pocket engineering: its impact on the electrical performance of a hetero-structure tunnel FET. Silicon 1:3. https://doi.org/10.1007/s12633-022-01707-6

    Article  CAS  Google Scholar 

  10. Talukdar J, Mummaneni K (2020) A non-uniform silicon TFET design with dual-material source and compressed drain. Appl Phys A Mater Sci Process 126:1–9. https://doi.org/10.1007/s00339-019-3266-5

    Article  CAS  Google Scholar 

  11. Tirkey S, Sharma D, Yadav DS, Yadav S (2017) Analysis of a novel metal implant junctionless tunnel FET for better DC and analog/RF electrostatic parameters. IEEE Trans Electron Devices 64:3943–3950. https://doi.org/10.1109/TED.2017.2730922

    Article  CAS  Google Scholar 

  12. Gupta AK, Raman A, Kumar N (2019) Design and investigation of a novel charge plasma-based core-shell ring-TFET: analog and linearity analysis. IEEE Trans Electron Devices 66:3506–3512. https://doi.org/10.1109/TED.2019.2924809

    Article  CAS  Google Scholar 

  13. Talukdar J, Rawat G, Singh K, Mummaneni K (2020) Comparative analysis of the effects of trap charges on single- and double-gate extended-source tunnel FET with δp+ SiGe pocket layer. J Electron Mater 49:4333–4342. https://doi.org/10.1007/s11664-020-08151-5

    Article  CAS  Google Scholar 

  14. Abdi DB, Kumar MJ (2014) Controlling ambipolar current in tunneling FETs using overlapping gate-on-drain. IEEE J Electron Devices Soc 2:187–190. https://doi.org/10.1109/JEDS.2014.2327626

    Article  Google Scholar 

  15. Kumar K, Chandra S (2022) Band gap and drain dielectric pocket engineered ­ Si 0 . 2 Ge 0 . 8 / GaAs junctionless TFET with dual dielectric gate for ambipolar suppression and electrical performance enhancement. Silicon. https://doi.org/10.1007/s12633-022-02192-7

    Article  PubMed Central  Google Scholar 

  16. Yadav R, Dan S, Vidhyadharan S et al (2021) Suppression of ambipolar behavior and simultaneous improvement in RF performance of gate-overlap tunnel field effect transistor (GOTFET) devices. Silicon 13:1185–1197. https://doi.org/10.1007/s12633-020-00506-1

    Article  CAS  Google Scholar 

  17. Dutta U, Soni MK, Pattanaik M (2019) Simulation study of hetero dielectric tri material gate tunnel FET based common source amplifier circuit. AEU - Int J Electron Commun 99:258–263. https://doi.org/10.1016/j.aeue.2018.12.004

    Article  Google Scholar 

  18. Panda S, Jena B, Dash S (2022) Ambipolarity suppression of a double gate tunnel FET using High-k drain dielectric pocket. ECS J Solid State Sci Technol 11:013014. https://doi.org/10.1149/2162-8777/ac4d82

    Article  Google Scholar 

  19. Choi WY, Lee W (2010) Hetero-gate-dielectric tunneling field-effect transistors. IEEE Trans Electron Devices 57:2317–2319. https://doi.org/10.1109/TED.2010.2052167

    Article  Google Scholar 

  20. Verhulst AS, Vandenberghe WG, Maex K, Groeseneken G (2007) Tunnel field-effect transistor without gate-drain overlap. Appl Phys Lett 91:053102. https://doi.org/10.1063/1.2757593

    Article  CAS  Google Scholar 

  21. Kumar K, Kumar A, Kumar V, Chander S (2023) International Journal of Electronics and Communications Band gap and gate underlap engineered novel Si 0 . 2 Ge 0 . 8 / GaAs JLTFET with dual dielectric gate for improved wireless applications. AEUE - Int J Electron Commun 166:154671. https://doi.org/10.1016/j.aeue.2023.154671

    Article  Google Scholar 

  22. Sharma S, Chaujar R (2021) Performance enhancement in a novel amalgamation of arsenide/antimonide tunneling interface with charge plasma junctionless-TFET. AEU - Int J Electron Commun 133:153669. https://doi.org/10.1016/J.AEUE.2021.153669

    Article  Google Scholar 

  23. Boucart K, Ionescu AM (2007) Double-gate tunnel FET with high-κ gate dielectric. IEEE Trans Electron Devices 54:1725–1733. https://doi.org/10.1109/TED.2007.899389

    Article  CAS  Google Scholar 

  24. Mallik A, Chattopadhyay A, Guin S, Karmakar A (2013) Impact of a spacer-drain overlap on the characteristics of a silicon tunnel field-effect transistor based on vertical tunneling. IEEE Trans Electron Devices 60:935–943. https://doi.org/10.1109/TED.2013.2237776

    Article  CAS  Google Scholar 

  25. Naderi A, Keshavarzi P (2012) The effects of source/drain and gate overlap on the performance of carbon nanotube field effect transistors. Superlattices Microstruct 52:962–976. https://doi.org/10.1016/j.spmi.2012.07.016

    Article  CAS  Google Scholar 

  26. Ram MS, Abdi DB (2015) Dopingless PNPN tunnel FET with improved performance: design and analysis. Superlattices Microstruct 82:430–437. https://doi.org/10.1016/J.SPMI.2015.02.024

    Article  CAS  Google Scholar 

  27. Kumar K, Kumar A, Sharma SC (2023) Electrical performance improvement of charge plasma-based junctionless TFET using novel coalescence of SiGe/GaAs and heterogeneous gate dielectric. Appl Phys A Mater Sci Process 129:23. https://doi.org/10.1007/s00339-022-06309-y

    Article  CAS  Google Scholar 

  28. Ghosh B, Akram MW (2013) Junctionless tunnel field effect transistor. IEEE Electron Device Lett 34:584–586. https://doi.org/10.1109/LED.2013.2253752

    Article  CAS  Google Scholar 

  29. Bal P, Akram MW, Mondal P, Ghosh B (2013) Performance estimation of sub-30 nm junctionless tunnel FET (JLTFET). J Comput Electron 12:782–789. https://doi.org/10.1007/S10825-013-0483-6/FIGURES/13

    Article  Google Scholar 

  30. MolaeiImenAbadi R, SedighZiabari SA (2016) Representation of strained gate-all-around junctionless tunneling nanowire filed effect transistor for analog applications. Microelectron Eng 162:12–16. https://doi.org/10.1016/J.MEE.2016.04.016

    Article  CAS  Google Scholar 

  31. Goswami Y, Asthana P, Ghosh B et al (2015) Temperature effect on hetero structure junctionless tunnel FET. J Semicond 36:034002. https://doi.org/10.1088/1674-4926/36/3/034002

    Article  CAS  Google Scholar 

  32. Bal P, Ghosh B, Mondal P et al (2014) Dual material gate junctionless tunnel field effect transistor. J Comput Electron 13:230–234. https://doi.org/10.1007/S10825-013-0505-4/FIGURES/6

    Article  CAS  Google Scholar 

  33. Xie H, Liu H, Wang S et al (2020) Improvement of electrical performance in heterostructure junctionless TFET based on dual material gate. Appl Sci 10(10):126. https://doi.org/10.3390/APP10010126

    Article  CAS  Google Scholar 

  34. Lahgere A, Panchore M, Singh J (2016) Dopingless ferroelectric tunnel FET architecture for the improvement of performance of dopingless n-channel tunnel FETs. Superlattices Microstruct 96:16–25. https://doi.org/10.1016/J.SPMI.2016.05.004

    Article  CAS  Google Scholar 

  35. Rahimian M, Fathipour M (2016) Asymmetric junctionless nanowire TFET with built-in n+ source pocket emphasizing on energy band modification. J Comput Electron 15:1297–1307. https://doi.org/10.1007/S10825-016-0895-1/TABLES/1

    Article  Google Scholar 

  36. Aghandeh H, SedighZiabari SA (2017) Gate engineered heterostructure junctionless TFET with Gaussian doping profile for ambipolar suppression and electrical performance improvement. Superlattices Microstruct 111:103–114. https://doi.org/10.1016/j.spmi.2017.06.018

    Article  CAS  Google Scholar 

  37. Raad BR, Sharma D, Kondekar P et al (2016) Drain work function engineered doping-less charge plasma TFET for ambipolar suppression and RF performance improvement: a proposal, design, and investigation. IEEE Trans Electron Devices 63:3950–3957. https://doi.org/10.1109/TED.2016.2600621

    Article  CAS  Google Scholar 

  38. Venkatasubramanian R, Timmons ML, Mantini M et al (1990) Heteroepitaxy and characterisation Of Ge-Rich SiGe alloys on GaAs. MRS Online Proc Libr 198:547–552. https://doi.org/10.1557/PROC-198-547

    Article  CAS  Google Scholar 

  39. Youssouf AS, Habaebi MH, Ibrahim SN, Hasbullah NF (2017) Gain Investigation for commercial GaAs and SiGe HBT LNA’s under Electron irradiation. Proc - 14th IEEE Student Conf Res Dev Adv Technol Humanit SCOReD 2016. https://doi.org/10.1109/SCORED.2016.7810094

  40. Han T, Liu H, Wang S et al (2019) Design and Investigation of the junction-less TFET with Ge/Si0.3Ge0.7/Si heterojunction and heterogeneous gate dielectric. Electron 8:476. https://doi.org/10.3390/ELECTRONICS8050476

    Article  CAS  Google Scholar 

  41. Asthana PK, Ghosh B, Goswami Y, Tripathi BMM (2014) High-speed and low-power ultradeep-Submicrometer III-V heterojunctionless tunnel field-effect transistor. IEEE Trans Electron Devices 61:479–486. https://doi.org/10.1109/TED.2013.2295238

    Article  CAS  Google Scholar 

  42. (2018) ATLAS User’s Guide, SILVACO Int., 5.26.1.R. Santa Clara, CA, USA

  43. Vadizadeh M (2021) Digital performance assessment of the dual-material gate GaAs/InAs/Ge junctionless TFET. IEEE Trans Electron Devices 68:1986–1991. https://doi.org/10.1109/TED.2021.3056632

    Article  CAS  Google Scholar 

  44. Hänsch W, Vogelsang T, Kircher R, Orlowski M (1989) Carrier transport near the Si/SiO2 interface of a MOSFET. Solid State Electron 32:839–849. https://doi.org/10.1016/0038-1101(89)90060-9

    Article  Google Scholar 

  45. Zhao Y, Wu C, Huang Q et al (2017) A novel tunnel FET design through adaptive bandgap engineering with constant sub-threshold slope over 5 decades of current and high ION/IOFF ratio. IEEE Electron Device Lett 38:540–543. https://doi.org/10.1109/LED.2017.2679031

    Article  CAS  Google Scholar 

  46. Zhou G, Lu Y, Li R et al (2011) Self-aligned InAs/Alo.45Ga0.55Sb vertical tunnel FETs. In: 69th device research conference. IEEE, pp 205–206

  47. Na KY, Kim YS (2006) Silicon complementary metal-oxide-semiconductor field-effect transistors with dual work function gate. Japanese J Appl Physics, Part 1 Regul Pap Short Notes Rev Pap 45:9033–9036. https://doi.org/10.1143/JJAP.45.9033/META

  48. Sharma S, Chaujar R (2022) Impact of tunnel gate process variations on analog/radio frequency (microwave) and small signal parameters of hetero-material tunneling interfaced charge plasma junctionless tunnel field effect transistor. Int J Circuit Theory Appl:1–16. https://doi.org/10.1002/cta.3347

  49. Johnson RW, Hultqvist A, Bent SF (2014) A brief review of atomic layer deposition: from fundamentals to applications. Mater Today 17:236–246. https://doi.org/10.1016/J.MATTOD.2014.04.026

    Article  CAS  Google Scholar 

  50. Talukdar J, Rawat G, Mummaneni K (2021) Dielectrically modulated single and double gate tunnel FET based biosensors for enhanced sensitivity. IEEE Sens J 21:26566–26573. https://doi.org/10.1109/JSEN.2021.3122582

    Article  CAS  Google Scholar 

  51. Brouzet V, Salem B, Periwal P et al (2015) Fabrication and characterization of silicon nanowire p-i-n MOS gated diode for use as p-type tunnel FET. Appl Phys A Mater Sci Process 121:1285–1290. https://doi.org/10.1007/S00339-015-9507-3

    Article  CAS  Google Scholar 

  52. Kumar K, Sharma SC (2022) Impact of band gap and gate dielectric engineering on novel Si 0 . 1 Ge 0 . 9 -GaAs lateral N-type charge plasma based JLTFET. Microelectronics J 130:105610. https://doi.org/10.1016/j.mejo.2022.105610

    Article  CAS  Google Scholar 

  53. Verma PK, Gupta SK (2021) An improved analog/RF and linearity performances with small-signal parameter extraction of virtually doped recessed source/drain dopingless junctionless transistor for radio-frequency applications. Silicon 13:1519–1539. https://doi.org/10.1007/S12633-020-00518-X

    Article  CAS  Google Scholar 

  54. Ghosh P, Haldar S, Gupta RS, Gupta M (2012) An investigation of linearity performance and intermodulation distortion of GME CGT MOSFET for RFIC design. IEEE Trans Electron Devices 59:3263–3268. https://doi.org/10.1109/TED.2012.2219537

    Article  Google Scholar 

  55. Das D, Chakraborty U (2021) Effect of dielectric pocket for controlling ambipolar conduction in TFET and analysis of noise and temperature sensitivity. Indian J Phys 96:795–809. https://doi.org/10.1007/S12648-021-02054-9/FIGURES/29

    Article  Google Scholar 

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Acknowledgements

All Authors would like to thank the Indian Institute of Technology, Roorkee, and Graphic Era Deemed to be University for their support and permission to communicate this research paper.

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Authors and Affiliations

  1. Microelectronics and VLSI Lab, Electronics and Computer Discipline DPT, IIT Roorkee, Roorkee, Uttarakhand, India

    Kaushal Kumar & Subhash Chander Sharma

  2. ECE Department, Graphic Era Deemed to be University, Dehradun, Uttarakhand, India

    Kaushal Kumar & Vinay Kumar

  3. ECE Department, Jaypee Institute of Information Technology, Noida, Uttar Pradesh, India

    Ajay Kumar

  4. Symbiosis Institute of Technology, Symbiosis International (Deemed University), Pune, Maharashtra, India

    Aditya Jain

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  1. Kaushal Kumar
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Contributions

Conceptualization: [Kaushal Kumar, Ajay Kumar]; Methodology: [Kaushal Kumar, Subhash Chander Sharma]; Formal analysis and investigation: [Kaushal Kumar, Vinay Kumar, Aditya Jain, Subhash Chander Sharma]; Writing - original draft preparation: [Kaushal Kumar]; Writing - review and editing: [Kaushal Kumar, Ajay Kumar, Vinay Kumar, Aditya Jain, Subhash Chander Sharma].

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Kumar, K., Kumar, A., Kumar, V. et al. Ambipolarity Suppression of Band Gap and Gate Dielectric Engineered Novel Si0.2Ge0.8/GaAs JLTFET Using Gate Overlap Technique. Silicon 15, 7837–7854 (2023). https://doi.org/10.1007/s12633-023-02624-y

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