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Ultra-Low-Power and Fast Voltage Level Shifter Using Muller C-Cell for VLSI Systems

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Abstract

The power efficiency is an extremely essential feature in the modern mobile computing and autonomous sensors node applications. Voltage scaling is the significant technique to attain power-efficient operation utilizing voltage level shifters. Level shifters (LSs) with high performance are vital interconnecting circuits to achieve compactness in the multiple-supply voltage low-power VLSI systems. This article presents a fast and ultra-low static power LS adopting Muller C-cell along with stacked inverter. In addition, the Muller C-cell-based level shifter (MCLS) uses a pass transistor and dynamic threshold MOS with INWE-aware device sizing to make stronger the pull-down network and Wilson current mirror/source in the pull-up network to support Muller C-cell for level shifting operation. The structure of Muller C-cell helps to achieve ultra-low standby power in addition to fast switching, as expected. The MCLS is implemented in 180 nm CMOS technology and its performance is evaluated through Spectre Circuit Simulator using Cadence (Virtuoso) platform. From the simulated results, it is observed that the MCLS takes delay of 2.4 ns and consumes energy of 127 fJ/transition for the level shifting from 500 mV to 1.8 V with input frequency (\(f _\mathrm{in} \)) of 1 MHz. It is also noted that the MCLS consumes static power of 47.7 pW at standby mode and it has the ability to convert lower input voltage of 410 mV to higher output voltage of 1.8 V. Furthermore, functionality of the MCLS is experimentally confirmed through prototype developed using IC HEF4007UBP and it ensures fast and wider voltage conversion.

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Data Availability

The authors declare that the data supporting the findings during this research work are available within the paper as listed in Tables 1, 2 and 3. The schematic of the work is developed on CADENCE platform (Virtuoso schematic editor) and the performance analysis is performed by creating simulation set-up in the Analog Design Environment (ADE) by choosing model libraries, Spectre Circuit Simulator with required stimulus details. In addition, parametric analysis tool is used and the simulated results are obtained on the waveform viewer.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Karpagam College of Engineering, Coimbatore, Tamil Nadu, 641032, India

    Selvakumar Rajendran & Arvind Chakrapani

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  1. Selvakumar Rajendran
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  2. Arvind Chakrapani
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Correspondence to Selvakumar Rajendran.

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Rajendran, S., Chakrapani, A. Ultra-Low-Power and Fast Voltage Level Shifter Using Muller C-Cell for VLSI Systems. Circuits Syst Signal Process 41, 6530–6546 (2022). https://doi.org/10.1007/s00034-022-02098-0

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  • DOI: https://doi.org/10.1007/s00034-022-02098-0

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