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Fast multiplication in VLSI using wave pipelining techniques

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Abstract

Wave pipelining is a design methodology that can increase the clock frequency of digital systems. Also known asmaximum-rate pipelining, it has long been considered a technique for approaching the physical speed limit of a digital circuit. Unlike conventional pipelining, wave pipelining does not require internal clocked elements to increase throughput. The synchronization of internal computations is achieved by balancing inherent RC delays of combinational logic elements, thus allowing circuits to be pipelined at a very fine-grain level. In this article, we describe the design of a 16×16 wave-pipelined multiplier using a 1.0 μm CMOS process. The multiplier is designed using a conventional static CMOS technology. Simulation results show a speedup of about 7× over a nonpipeline implementation.

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Authors and Affiliations

  1. Laboratory for Computer Architecture and Digital Systems, Delft University of Technology, 2600 GA, Delft, The Netherlands

    Fabian Klass & Ad J. Van De Goor

  2. Computer Systems Laboratory, Stanford University, 94305-4055, Stanford, California

    Michael J. Flynn

Authors
  1. Fabian Klass
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  2. Michael J. Flynn
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  3. Ad J. Van De Goor
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Klass, F., Flynn, M.J. & Van De Goor, A.J. Fast multiplication in VLSI using wave pipelining techniques. Journal of VLSI Signal Processing 7, 233–248 (1994). https://doi.org/10.1007/BF02409400

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  • DOI: https://doi.org/10.1007/BF02409400

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