Abstract
Inversion is a significant operation in ECC processors and is the most complex and time-consuming operation among operations like addition, subtraction and multiplication. Thus, proposing an algorithm and designing its architecture to compute inverse with minimum number of clock cycles are mandatory. In this brief, high-speed inversion of NIST recommended pentanomial \(\text {GF}(2^{163})\), based on traditional Itoh–Tsujii inversion algorithm (ITIA) is proposed. This proposed inversion algorithm is then implemented on FPGA Virtex-5 platforms to analyze its performance. This design minimizes the latency and, thereby, improves speed. The developed high-speed Itoh–Tsujii inversion algorithm HS-ITIA computes inversions in 18 clock cycles with maximum clock frequency 64.5 MHz, which thereby yields a rise in performance by 56%.
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Kalaiarasi, M., Venkatasubramani, V.R., Christina Grace, A., Rajaram, S. (2020). High-Speed Inversion Using \(x^{4^{n}}\) Units. In: Jayakumari, J., Karagiannidis, G., Ma, M., Hossain, S. (eds) Advances in Communication Systems and Networks . Lecture Notes in Electrical Engineering, vol 656. Springer, Singapore. https://doi.org/10.1007/978-981-15-3992-3_50
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DOI: https://doi.org/10.1007/978-981-15-3992-3_50
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